STM32F072 lowest PCLK is 10MHz?

[ingenieria]

Posted on July 31, 2015 at 12:26

We have a design with STM32F072, and we would like to work with HSI at 8MHz in order to achieve the lowest posible consumption as long as we don't need too much processing power, thus the USB requiring 48MHz would be clocked from HSI48.

So we profile with STMCUBEMX, to have HCLK and PCLK at 8MHz, we have a red hint on the clock configuration screen that says that PCLK must be between 10MHz and 48MHz, the issue is that i can't find the reason of having PCLK higher to 10Mhz in any document of STM32F0 family , can someone explain us why this hint, or at least where to find this information?

Thank you in advance

[Tesla DeLorean]

Posted on July 31, 2015 at 17:11

From RM0091

''Note:Due to USB data rate and packet memory interface requirements, the APB clock must have a minimum frequency of 10 MHz to avoid data overrun/underrun problems.''

This suggests ST has validated this operation, and there are known issues with latency or servicing below the threshold.

More generally these problems stem from a ''clock inversion'' issues, where the synchronization between clock domains where one bus is expected to be the same or greater than another. Logic to manage the discrepancy in clock speeds usually just works in one direction.

[ingenieria]

Posted on August 01, 2015 at 00:21

Thank you clive, so my solution is to use PLL only when USB 5V are detected, so the rest of the time when battery operated i can freely work  with PCLK 8MHz.