Squarewave out to PF.15

[bikejog]

Posted on July 31, 2013 at 05:48

Howdy,

    Need to output a 25kHz squarewave.  Besides the obvious using a timer ISR, what other ways this can be accomplished?

1. Timer PWM?  As far as I know, no timer can output a PWM out to PF.15.  Am I wrong?

2. DMA from Flash (or RAM) memory to PORTF->BSRR.  I was able to get this to work, however I'm wondering if the DMA transaction to the BSRR register is guaranteed to be atomic if the CPU accesses the same port at the same time that the DMA transaction is in progress?  I know when the CPU accesses the BSRR, the operation is guaranteed to be atomic.  Does this guaranteed also applies to DMA?

TIA

Andy

#dma-gpio

[Tesla DeLorean]

Posted on July 31, 2013 at 17:43

On what processor? The STM comes in half a dozen series.

For the F2/F4, yes there is no timer output, not sure what ''EVENTOUT'' is, or if it can be exploited.

The DMA is going to have arbitrated it's own access if you are in 32-bit (WORD) mode, I don't see BSRR being an issue in that regard. The memory read, and peripheral write, may well not be atomic but I don't see that impacts anything, the RMW operation on the GPIO output is buried in the internal logic for the WRITE on BSRR, and nothing to do with the pattern read from memory.

I'd probably suggest doing the DMA from RAM, as the wait-states on the FLASH will kill you every time, as this won't be cached or prefetched, as best I can tell.

[bikejog]

Posted on July 31, 2013 at 18:30

The Part is STM32F103ZE.  I don't need atomic operation between memory and the GPIO, but must be atomic on the GPIO port pins themselves.  

BSRR writes are atomic across high level code and ISRs so is it safe to assume that it will also be atomic across bus masters?

Which doc did you see the GPIO drawing regarding to RMW to GPIOs?

Also, my DMA1 now has 2 channels used up and one of them is the ADC at 1.5 cycles of conversion  time which amounts to about a 1.3 uSecs period.  Having 2 channels used takes about 250nSecs of that time in the worst case.  I know that the DMA will stall if the CPU tries to access APB2 at the same time.  Do you know what's the maximum APB access time from the CPU because this will add to the worst case DMA latency.

TIA

Andy

[Tesla DeLorean]

Posted on July 31, 2013 at 19:03

The Set/Reset behaviour of BSRR is achieved with logic within the GPIO peripheral, it's not a ''memory'' access in the classic sense. ie the flip-flops holding ''ODR'' for the bank latch a new state driven by your set/reset request, and the looped back current state. The latching will be synchronous with the APB/AHB, other pending writes will occur sequentially afterward, and in program order.

Not sure this is in the manual, the HDL is probably not available.

It will be something like

ODR[x] := (ODR[x] OR SET[x]) AND !RESET[x];