spi master to parallel (not cascade) 74hc595

[gds2]

Posted on September 26, 2009 at 16:45

spi master to parallel (not cascade) 74hc595

[sofiene]

Posted on May 17, 2011 at 13:24

Hi gds;

Which pin are you talking about? the output of the internal shift regsier i.e. pin 9 (Q7')? or the 8 pins o the latch register (Q0-Q7)?

[gds2]

Posted on May 17, 2011 at 13:24

I am trying to use the stm32 spi master output to talk to 2 parallel connected 74hc595 shift registers. They share the output enable, sclk, MOSI. But they each have a separate latch clock. So when a byte is shifted out the MOSI port, it is shifted into each register with the common sclk line. But the latch clocks, acting as sort of a chip select, latch the output of the selected 74hc595.

This is different that the usual way multiple 74hc595's are cascaded in a chain.

My problem is that I often see the same data latched to the output on the same pin of both shift register devices even though I am only toggling the latch clock (low to high) on one of the devices.

Has anyone done a similar project with 74hc595's connected in ''parallel'' that works?

[gds2]

Posted on May 17, 2011 at 13:24

Quote:

On 23-09-2009 at 11:20, Anonymous wrote:

Quote:

On 23-09-2009 at 05:34, Anonymous wrote:

even though I am only toggling the latch clock (low to high) on one of the devices.

You said that you toggle the latch clock (low to high) to latch the data in the output register, but the data is loaded into the shift register when OE\ goes from high to low and not low to high. So during the phase of the data shifting into the shift register OE\ (of the two 74hc595)should be at the High level: the two internal shift registers of the two 74hc595) are loaded with the same data. When this phase is achieved, you toggle OE\ of the desired 74hc595 from high two low then low to high, and you keep the OE\ of the second 74hc595 at high level.

Hope that this will helpful.

The two 595s receive the following same signals:

sclk

oe/

Data In (MOSI on spi bus)

The two 595's have a unique signal that selects which one latches to its output the byte received on Data In (they both shift in the same value):

latch clock A

latch clock B

When the respective latch clock goes low->high it latches (clocks) the shifted in byte to the output register of only the selected 595. For the output register to appear on the outputs, common oe/ must be brought low.

The overflow output (for cascading) is not used in this h/w design (which I didn't do).

[sofiene]

Posted on May 17, 2011 at 13:24

Quote:

On 23-09-2009 at 05:34, Anonymous wrote:

even though I am only toggling the latch clock (low to high) on one of the devices.

You said that you toggle the latch clock (low to high) to latch the data in the output register, but the data is loaded into the shift register when OE\ goes from high to low and not low to high. So during the phase of the data shifting into the shift register OE\ (of the two 74hc595)should be at the High level: the two internal shift registers of the two 74hc595) are loaded with the same data. When this phase is achieved, you toggle OE\ of the desired 74hc595 from high two low then low to high, and you keep the OE\ of the second 74hc595 at high level.

Hope that this will helpful.

[gds2]

Posted on May 17, 2011 at 13:24

The problem was due to some emi filtering blocking the latch clock to one of of the 595's. So it works now as I expect. Thanks for the helpful comments.

[gds2]

Posted on May 17, 2011 at 13:24

Quote:

On 23-09-2009 at 11:02, Anonymous wrote:

Hi gds;

Which pin are you talking about? the output of the internal shift regsier i.e. pin 9 (Q7')? or the 8 pins o the latch register (Q0-Q7)?

I see the same bits on Q0-Q7 of both 595s. I am not using the output/overflow/cascade pin 9 at all. Both 595's receive the same byte value on the SPI byte transmission but only the selected 595 latches the value to its outputs using a low->high on latch clock (pin 12). So pin 12 acts as kind of an edge-triggered chip select.

OE/, common to both 595s, is typically just low so that outputs appear and not high-impedance outputs. It does not act as a chip select itself.

[jj_it]

Posted on May 17, 2011 at 13:24

Believe that poster is correct - that 595 ''loads/latches'' its outputs on a low to high transition on pin 12. (sorry m3allem)

For you to clock ''both'' 595's from a correct, unique STM32 output must mean:

a) Your STM32 ''non-designated'' output is not truly/properly pulling its 595 clock pin low - while the ''designated'' output is strobing high.

or

b) You have short between designated and non-designated traces

or

c) You have ''coupling'' between these traces or between STM32 outputs.

Cure:

Scope the non-designated input while you provide say 50Hz pulses to

the designated input. This will reveal the extent of the problem.

Carefully - I would change the non-designated input (STM32) pin from output to input - and only then ''tack ground'' this pin @ the 595. Now this 595 should never be able to load its latch. If indeed - this proves to be the case - you need to filter (small cap) or instruct STM32 to better drive its ''non-designated'' output to ground.

Respondez - s'il vous plait...

[jj_it]

Posted on May 17, 2011 at 13:24

Glad you found a ''fix'' - however it is doubtful that ''simultaneous, double pulsing'' was caused by ''blocking'' the undesignated 595 latch clock. (as it responded every time to your pulse!) Our $$$ still rides on a simple short between designated/undesignated...