SPI bus clock routing and termination scheme

[jbourgeois]

Posted on June 26, 2015 at 03:37

SPI2 out of my STM32 has 3 destinations: header, i/o expander, and FPGA.  I have a single series termination resistor on this clock.  Should I route this in a daisy-chain fashion with stops at each location that minimizes stubs?  Should I make 3 copies?  Etc. 

The current routed length for the whole bus is 8.7 inches.

Any experience that can be shared regarding doing this with SPI clocks would be most appreciated!

#spi #st32m