RNG clock error on NUCLEO-L4A6ZG

[JKo]

I am trying to use the RNG on the STM32L4A6ZG but every time I enable the RNG clock RNG_CR |= RNGEN the RNG_SR shows CEIS and CECS.

The AHB bus is at 80MHz and RNG_CLK is at 48MHz. I've tested with configuring the RNG_CLK to come from either the HSI48 or PLL48M2CLK by setting RCC_CCIPR CLK48SEL accordingly.

The RNG peripheral clock RCC_AHB2 |= RNGEN is also enabled.

PLL source is set to HSI16

PLL M = 1

PLL N = 20

PLL R = 4

PLL R output is enabled

SYSCLK source is set to PLLCLK

AHB PRESC is 1

PLLSAI1 N = 18

PLLSAI1 Q = 6

PLLSAI1 Q output is enabled

The problem seems to be related to either the HSI16 or the STM32L4A6ZG itself since I can configure and use the RNG on a custom board with an STM32L4A6RG but with a TCXO at 8MHz. PLL M = 2 and N = 80, PLLSAI1 N = 72, other values are the same as above.

I have also tried disabling the CED by writing 1 to RNG_CR.CED bit (with the RNGEN=0), but reading back the RNG_CR always shows CED=0.

Any ideas on what my problem could be? Something else I could try?

[waclawek.jan]

> every time I enable the RNG clock RNG_CR |= RNGEN the RNG_SR shows CEIS and CECS.

And the other 3 status bits?

Can CEIS and CECS be cleared?

Is HSI16 running?

Read out and post content of all RCC and RNG registers.

JW

[JKo]

Yes. HSI16 is running. The board and the USART peripherals wouldn't come up otherwise.

It did point me to look at the PLLSAI1 in the RCC_CR however and I found that was not enabled!

Turns out that on my other device which has USB enabled, the PLLSAI1 clock was enabled already but since I'm replacing the USB interface with a UART interface the PLLSAI1 clock wasn't enabled.

The HSI48 clock also required HSI48ON in the RCC_CRRCR if that source was selected.

Thanks.