Relation between JTAG/SWD and HCLK

[Uwe Bonnes]

Posted on May 19, 2016 at 11:50

Hello,

I am searching for hard facts about the clock relation requirements between the Core HCLK Clock and the external applied JTAG/SWD clock. Any hints welcome!

[Tesla DeLorean]

Posted on May 20, 2016 at 03:42

Does there need to be? In scan chain architectures I'm familiar with the scan side of the flip-flop is independent, and load/store to the active side occurs when things are stopped.

The SWO (SWV) data stream is dependent on the core clocking to configure its ''baud rate'', and is synchronous, rather than externally clocked.