Low Power Mode StandBy at STM32L562 - SRAM2 Data retention cannot be disabled

[MPetr.3]

Hello Community,

I am programming the STM32L562E-DK discovery board and working with the Standby low-power mode. In the data sheet there are 3 standby variations explained:

• Standby with Full SRAM2 data retention
• Standby with 4kB SRAM2 data retention
• Standby without any data retention (all SRAM1 and SRAM2 is lost)

I cannot reach the variations, where part of the SRAM2 or all SRAM2 data retention should be disabled.

Always after I wake up the processor from the standby mode the data in SRAM2 is still there. SRAM1 is lost (which is correct).

I have tried everything to activate the Standby mode without any data retention, but it doesnt work.

To put the processor in standby mode I use the following code:

__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_SB);
if (__HAL_PWR_GET_FLAG(PWR_FLAG_WUF2) != RESET)/* Check and Clear the Wakeup flag */
{
	__HAL_PWR_CLEAR_FLAG(PWR_FLAG_WUF2);
}
HAL_PWR_EnableWakeUpPin(PWR_WAKEUP_PIN2_HIGH);
__HAL_PWR_CLEAR_FLAG(PWR_FLAG_WUF2);
HAL_PWREx_EnableUltraLowPowerMode();
HAL_PWREx_DisableSRAM2ContentRetention();
HAL_PWR_EnterSTANDBYMode();

I checked every important register, especially the PWR->CR3->RRS bits which determine SRAM2 data retention.

My code is pretty much based on the official standby mode example at https://github.com/STMicroelectronics/STM32CubeL5/blob/master/Projects/STM32L562E-DK/Examples/PWR/PWR_STANDBY/Src/main.c .

I don't know if I am missing an instruction or if there exists a hardware bug which leads to the disability to disable SRAM2.

If anyone can help I would very much appreciate it.

Thanks in advance.

[Mike_ST]

Please check L5x2 errata stheet :

https://www.st.com/en/microcontrollers-microprocessors/stm32l5x2.html#documentation

There is one item talking about SRAM2 and standby, but I didn't check if it matches your case.

[MPetr.3]

Thank you for your answere Mike.

I have checked the errata sheet but sadly this is not the case.

It says :

Since I am directly transitioning from run mode to standby "with" modes, I don think this errata is valid for my case.

I am still looking for a solution.

[MLint.1]

I have seen this too. Ie, SRAM2 data being retained when the RRS bits are clear. i read them back to check. What bought me here is the converse,  and for me, a very serious problem. The RRS bits are set for 4 k SRAM2 retention, and after a period of weeks or months, the product is acting as though SRAM2 data retention through standby has failed, SRAM2 being filled with pseudo random garbage on wake from standby.