Is it possible to determine PWM of 0% or 100% duty cycle?

[Richard Cooke]

Posted on November 17, 2017 at 01:32

Hi Folks,

I'm using the Nucleo32L031K6 and the PWM on TIM2 is working fine except when the signal goes to zero.  The input capture interrupt is called when the input changes but if it never changes how can I determine that? In my application I need to know the on time of the pulse which is captured in TIM2->CCR2.  If the input is removed quickly enough the TIM2->CCR2 register retains the old value and never goes to zero. Is there a 'standard' way to solve this issue?

Thanks in advance,

Richard

#pwm-input

[Tesla DeLorean]

Posted on November 17, 2017 at 02:24

Keep the prescaler as small as possible. Use CCR3 or 4 to generate a timeout when no signal has been seen during normally expected period. ie CNT hit some outlying phase target.

[Richard Cooke]

Posted on November 17, 2017 at 03:34

Thanks Clive.  I'm a bit behind the power curve on your answer.  I'm using TIM2 for the PWM input so I'm using CH1 & CH2 to read the pulse width (CCR1 & CCR2 are used).  And it's working great but I'm a bit lost on how to setup the CCR3 to get triggered and to set the CNT to trigger an interrupt, if that's what you're suggesting.  Do you know of an example I could study?

Thanks again,

Richard

[Tesla DeLorean]

Posted on November 17, 2017 at 14:11

The TIM->CNT ticks at the rate you specify, the channels are independent, you can use PWM Input on Channel 1/2, and use Capture/Compare on Channel 3, so if you expect to see a pulse within 30000 cycles of the timebase then set TIM->CCR3 = 30000, and trigger on CC3 when no signal is present, ie CC3 fires when TIM->CNT == TIM->CCR3 regardless of what you choose to do with CCR1/CCR2

[S.Ma]

Posted on November 17, 2017 at 04:17

Use the timeroverflow (update) to timeout when the incoming frequency signal is too low

[Richard Cooke]

Posted on November 17, 2017 at 05:16

I must have spent way too long staring at my screen but can you point me in the right direction?  What register controls the timeroverflow?  And how do I set that up to trigger an interrupt?

[Richard Cooke]

Posted on November 19, 2017 at 00:53

Clive,

I'm using the CubeMX to help me generate the code so maybe that's why I'm not following you.  Since I'm using Ch1&Ch2 of TIM2 as the PWM input I have limited options for Ch3 or Ch4.  In the CubeMX setup for TIM2 Ch3 is disabled for inputs and Ch4 will use PA3 as an input pin but my PWM signal is connected to PA0.

I think what I want to do in a general way is:

Start the PWM input timers (Ch1&Ch2).  Every time a pulse is received on PA0, reset the counter for Ch4 timer.  If no pulse comes in and the counter overflows initiate an interrupt.  Is this possible?  And if it is how would I set this up?  I'm having trouble understanding how to make Ch4 trigger the INT.

Thanks,

Richard

[S.Ma]

Posted on November 19, 2017 at 03:32

Stoneage timer with just one input capture channel.

Let's say the lowest frequency of incoming PWM signal is 1 Hz. ok?

Program the timer as free running increment and overflow at 0xFFFF = 1 second.

Your measurement accuracy will be 1/65535th of a second.

Program the input capture on ANY edge AND program the timer to interrupt when overflow (whatever the name is).

When an edge occur, in the interrupt, you capture the timer value, read the GPIO to know if it was falling or rising edge, save the information in a global variable. If after 2 overflow interrupts both rising and falling edge capture did not get updated, it means the signal has been removed. Here we use the TIMER overflow as a timeout to use as little HW resource as possible.

Of course, this can be improved and perfected, by using a compare to program a precise time limit for the second capture to run. It's up to you to refine this concept.