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matic
Associate III
December 20, 2015
Question

Interrupt pending bits - what they are for?

  • December 20, 2015
  • 4 replies
  • 2523 views
Posted on December 20, 2015 at 19:42

If you have EXTI interrupt enabled, do you need to clear also pending bit in NVIC registers, when interrupt occurs? Or is it enough to clear bit in EXTI_PR register? I don't really understand what those pending bits in NVIC registers are for.

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    4 replies

    Tesla DeLorean
    Guru
    December 20, 2015
    Posted on December 20, 2015 at 20:23

    They are there for the NVIC to hold state and dispatch/prioritize the IRQHandlers. The mechanics let the NVIC clear its state and call the IRQHandler, then review the situation as the IRQHandler exits, or earlier for preemption.

    The peripherals typically latch their state and OR a number of internal sources together and feed one IRQ line to the NVIC. The peripherals bits either auto-clear, ie read of USARTx->DR changes the state, or must be clear explicitly, ie EXTI

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    matic
    maticAuthor
    Associate III
    December 20, 2015
    Posted on December 20, 2015 at 21:12

    So, if I understand correctly --> when EXTI interrupt occurs, I should clear flag in EXTI->PR register and also have to clear appropriate pending bit in NVIC register?

    And what in case of timer output compare interrupt? I always clear only CCIF inside of interrupt routine. Is this sufficient?

    Thanks

    Tesla DeLorean
    Guru
    December 20, 2015
    Posted on December 21, 2015 at 00:48

    So, if I understand correctly --> when EXTI interrupt occurs, I should clear flag in EXTI->PR register and also have to clear appropriate pending bit in NVIC register?

     

     

    And what in case of timer output compare interrupt? I always clear only CCIF inside of interrupt routine. Is this sufficient?

    Apparently not, as I just stated the flags in the NVIC are for its own benefit. So to reiterate you only need to clear it on the peripheral side.

    A side-effect of this is that you need to clear it on the peripheral side early in the handler, because due to it being a pipelined processor, with a write buffer, the interrupt is still signalling to the NVIC for several cycles, and you have to provide sufficient separation between that and the exit so it doesn't immediately tail-chain back into the same handler.

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    matic
    maticAuthor
    Associate III
    December 21, 2015
    Posted on December 21, 2015 at 06:35

    Ok, thank you very much. This makes things clear to me.