Question
Injected ADC Conversion Time off by 1.2usec
Posted on February 20, 2014 at 16:37
I am using TIM1 (PWM Mode) to trigger injected adc conversions in dual mode. The ADC clock is set to 72 Mhz (PLL Clock). The ADC sampling is set to 19.5 cycles --> a total conversion time of 19.5 + 12.5 = 32 cycles = 444 nsec. For N channels the JEOS interrupt should occur at N * 444 nsec after the rising edge of the PWM.
The problem is that the JEOS interrupt occurs at N * 1.68 usec after the rising edge of the PWM. I have tried this for 1,2 and 3 ADC conversions in the sequence. I have confirmed the correct clock by calling RCC_GetClocksFreq(). I also changed the sampling from 19.5 cycles to 61.5 cycles and the time from PWM rising edge to JEOS changed by the appropriate amount - 578 nsec. Does anyone know what's causing the 1.2usec delay in the ADC conversion