Init SRam with Zero for SRamParityChecking

[klaus2]

Posted on October 31, 2014 at 14:09

I use STM32F030F4 and want to use SRam-parity-checking. The reference manual hints:

''When enabling the RAM parity check, it is advised to initialize by software the whole RAM memory at the beginninng of the code, to avoid getting parity errors when reading non- initialized locations.'' I found in the startup_stm32f0xx.s(code below) something what maybe has something to with it. I think the SRAM is divided into 4 sections: data, bss, heap and stack. How could I initialize these sections for correct parity checking ? Sorry, Iam not really familiar with this basic things in ?Assembler?

Stack_Size EQU 
0
x
00000400
AREA STACK, NOINIT, READWRITE, ALIGN=
3
; How to init with zero ?
Stack_Mem SPACE Stack_Size
__initial_sp
......
.....
;*******************************************************************************
; User Stack and Heap initialization
;*******************************************************************************
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R
0
, = Heap_Mem
LDR R
1
, =(Stack_Mem + Stack_Size)
LDR R
2
, = (Heap_Mem + Heap_Size)
LDR R
3
, = Stack_Mem ; Maybe I can initialize them here with zero ?
BX LR
ALIGN
ENDIF

#sram #paritycheck #stm32f0

[Tesla DeLorean]

Posted on October 31, 2014 at 14:19

The linker is not going to initialize memory. You'd want to add code right at the ResetHandler entry point to go from 0x20000000 thru 0x20003FFF (or whatever the memory size is on your part) writing zero, or something, into the memory cells.

[Tesla DeLorean]

Posted on October 31, 2014 at 14:26

ldr r1, =0x20000000
ldr r2, =0x20004000
movs r3, #0
zeroloop
str r3, [r1]
adds r1, r1, #4
cmp r1, r2
bcc zeroloop

[klaus2]

Posted on October 31, 2014 at 14:38

Where do I have to place this code? In the startup file(stm32f0xx.s) is a section where the reset handler is called.  .....

; Reset handler routine

Reset_Handler PROC

EXPORT Reset_Handler [WEAK]

IMPORT __main

IMPORT SystemInit

LDR R

0

, =SystemInit

BLX R

0

LDR R

0

, =__main

BX R

0

ENDP

.....

  I also use global variables with initialisation. They should not be overwritten. I want to zero out the whole sram before global variables, etc. will be initialised.

[Tesla DeLorean]

Posted on October 31, 2014 at 15:51

.....
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit 
; >>>>>> RIGHT HERE <<<<<<
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
.....

''You'd want to add code right at the ResetHandler entry point'' I also use global variables with initialization. They should not be overwritten. I want to zero out the whole sram before global variables, etc. will be initialized. Where do you think this happens? The processor doesn't magically make this happen, the first instructions the processor executes are those pointed to by the Reset vector.

[klaus2]

Posted on October 31, 2014 at 16:11

Thank you. I wanted to ask to place it right there where you showed me now. So I got the answer before asking :-). First I had to understand what your asm code is doing and modified the sramsize for my target.

ldr r1, =0x20000000 ; load r1 with SRAM base address
ldr r2, =0x20000800 ; load r2 with SRAM end address(=2kb)
movs r3, #0 ; cpy 0 to r3 and update N=0 and z=1 flag #x(0<=x<
255
) 
zeroloop
str r3, [r1] ; store value of r3 at address 0x2000...
adds r1, r1, #4 ; 
r1
=r1+4 4byte(32bit word) (
N
=
0
,
Z
=
0
,
C
=
0) 

cmp r1, r2 ; compare r1 with r2
bcc zeroloop ; Go to label ''zeroloop'' if ''r1'' < ''r2''
;... Execution continues here if ''r1'' >= ''r2''

Further for basic understanding. I think you also answered this. When power up the mcu at first it will enter the reset handler?! Then it would make sense if the global variables will be initialised entering main application ?!

[Tesla DeLorean]

Posted on October 31, 2014 at 17:00

__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
..

The first thing the processor does is load an initial SP and PC from the vector table, execution proceeds from there. So the address of whatever routine you DCD there. In Keil the __main routine initializes the statics, either zeroing or copying/decompressing as appropriate, it also sets up the stack pointer before jumping to your main() routine.

[klaus2]

Posted on October 31, 2014 at 17:16

Thanks thats helpful!

Another error occured after compiling: ''...\startup_stm32f0xx.s(135): error: A1163E: Unknown opcode zeroloop , expecting opcode or Macro''

zeroloop: ; the '':'' does not fit the error
str r3, [r1] ; store value of r3 at address 0x2000...
adds r1, r1, #4 ; r1=r1+4 N=0,Z=0,C=0
cmp r1, r2 ; compare r1 with r2
bcc zeroloop ; Go to label ''zeroloop'' if ''Reg1'' < ''Reg2''
;... Execution continues here if ''Reg1'' >= ''Reg2''

[Tesla DeLorean]

Posted on October 31, 2014 at 17:25

I didn't use a colon there for a reason, Keil doesn't use GNU/GAS syntax

..\startup_stm32f072.s(135): error: A1167E: Invalid line start

Depending on columns Keil might give different errors, can't really do anything about that from here.

[klaus2]

Posted on October 31, 2014 at 17:32

zeroloop must begin in the first column. Then no error occurs.

; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit 
ldr r1, =0x20000000 ; load r1 with SRAM base address
ldr r2, =0x20000800 ; load r2 with SRAM end address(=2kb)
movs r3, #0 ; cpy 0 to r3 and update N=0 and z=1 flag #x(0<=x<
255
) 
zeroloop
str r3, [r1] ; store value of r3 at address 0x2000...
adds r1, r1, #4 ; 
r1
=r1+4 
N
=
0
,
Z
=
0
,
C
=
0
cmp r1, r2 ; compare r1 with r2
bcc zeroloop ; Go to label ''zeroloop'' if ''Reg1'' < ''Reg2''
;... Execution continues here if ''Reg1'' >= ''Reg2''
; Init the MCU and branch to main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP

Learned a lot from this. Thx

[Tesla DeLorean]

Posted on October 31, 2014 at 18:13

Can anyone from ST provide any more details on the parity/hamming schemes used on RAM and FLASH in the parts?