I²C Level Shifting Required for STM32L4?

[HermannKleier]

Posted on August 10, 2016 at 10:00

I operate an STM32L4 at 1.8 V and I�C peripherals at (up to) 3.6 V. The data sheet (DocID028794 Rev 2, table 21) is pretty clear when it comes to FT_xx inputs. But when it comes to FT_xx outputs I trip over the following statement:

The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are not �true�

 

open-drain. When configured as open-drain, the PMOS connected between the I/O pin and V_DDIOx is disabled, but is still

 

present.

What can I make of it? Does the (deactivated!) PMOS sink current from the 3.6 V I�C line to the 1.8 V V_DD-supply  because the MCU cannot drive its gate higher than V_DD? Where is the reference in the data sheet telling me that an open-drain output (FT_xx of course) can be raised above V_DD?

#i2c-stm32l4-ft_xx-5vtolerant

[Walid FTITI_O]

Posted on August 11, 2016 at 15:17

Hi kleier.hermann,

Take a look to ''Table 60. Output voltage characteristics'', I think that ''VOI FM+'' value gives you what you need to know.

-Hannibal-

[HermannKleier]

Posted on August 12, 2016 at 14:05

Table 60 describes the port output voltages when sinking/sourcing currents.

However, the question was about the FT_xx port output of a low-voltage (1.8 V) STM32L4xx configured open-drain without an internal(!) pull-up and connected via an external(!) pull-up to the interface voltage (3.6 V). How will the PMOS in Figure 19 (Basic structure of a five-volt tolerant I/O port bit, RM0394, DocID027295) behave? Note that then the PMOS is reverse-powered meaning that its drain (≈ 3.6V) is more positive than its source (VDDIOx ≈ 1.8V). To disable the PMOS, its gate voltage should be around 3.6 V. Does the somewhat menacing statement “but is still present� mean that it could pull the interface line down?

Or to ask it more practically:

Do I require a level shifter (see e.g. www.nxp.com/documents/application_note/AN10441.pdf) when I interface a low-voltage (1.8 V) STM32L4xx to a high-voltage (3.6 V) I²C device?

 

 

From: Hannibal

Posted: Thursday, August 11, 2016 3:17 PM

Subject: I²C Level Shifting Required for STM32L4?

Hi kleier.hermann,

Take a look to ''Table 60. Output voltage characteristics'', I think that ''VOI FM+'' value gives you what you need to know.

-Hannibal-

[Bertrand DENIS]

Posted on August 31, 2016 at 15:11

Hi,

To clarify: you don't need a level shifter  when interfacing a low-voltage (1.8 V) STM32L4xx to a high-voltage (3.6 V) I²C device.

Regards,

bdenis