HI, I programmed F103RB with SW4STM32 as following. LED is blinking as expected but I have Following Confusions/Questions. In Status Register flags for OCx for all channels are set however chanels are not enabled.

[WRaso.1]

#include "stm32f10x.h"

#include "stm32f10x_rcc.h"

#include "stm32f10x_gpio.h"

#include "stm32f10x_tim.h"

int main(void)

{

GPIO_InitTypeDef GPIO_InitStructure;

GPIO_StructInit(&GPIO_InitStructure);

RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5;

GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;

GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;

GPIO_Init(GPIOA, &GPIO_InitStructure);

//Timer-2 Configuration as

//As Up-Counter CMS=00 (edge aligned mode)

// OCx channels configured as output and disabled

RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2, ENABLE);

TIM_TimeBaseInitTypeDef TIMER2_TIME_BASE;

TIM_TimeBaseStructInit(&TIMER2_TIME_BASE);

TIMER2_TIME_BASE.TIM_CounterMode = TIM_CounterMode_Up;

TIMER2_TIME_BASE.TIM_Prescaler = 0xFFFF;

TIMER2_TIME_BASE.TIM_Period = 5490;

TIM_TimeBaseInit(TIM2, &TIMER2_TIME_BASE);

TIM_Cmd(TIM2, ENABLE);

while(1)

{

if (TIM2->SR & 0x00000001)

{

TIM2->SR ^= 0x00000001;

GPIOA->ODR ^= 0x000000020;

}

}

}

[TDK]

You can enable/disable the timer, but you cannot disable individual channels. They are always active when the timer is enabled. If you don't care about them, no need to worry about their flags getting set.

[WRaso.1]

Thanks for your answer, I was confusing CCxE bits in CCER registers as channel enable/disable bits.

While I tried different register settings to find some answer I found out that CCxIF are not set when CCRx=0x00000000 and CMS=01 in CR1. why is that ?

Also CNT value is never > ARR=1572 but CCxIF still set even I made CCRx=0x0000FFF0. Kindly answer these so that I understand TIMERs concepts.

Regards

[TDK]

@WRaso.1​  I suggest reading the reference manual section on timers. It is quite comprehensive.

[waclawek.jan]

See Figure Center-aligned PWM waveforms for the behaviour of CCxIF in up-down mode with CCRx=0.

Also, for CCRx>ARR, from description of TIMx_SR.CC1IF:

When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit 

goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow 

(in downcounting mode)

JW