Hi, I'm designing a board with STM32F417IEH6 using external clock which enters the internal PLL for generating SYSCLK. My question is, what happens when the external clock stops? does the PLL continues to work? does SYSCLK still exists? Thank you,

[EOvad.1]

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[TDK]

If your input to the PLL stops, your PLL will stop as well.

However, the STM32F4 has a clock security system which can trigger when HSE fails. You can use this to recover gracefully from a clock failure. From the reference manual (RM0090):

Clock security system (CSS)

The clock security system can be activated by software. In this case, the clock detector is

enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.