Ethernet MAC working while running wfi() ?

[spam3]

Posted on November 11, 2009 at 13:48

Ethernet MAC working while running wfi() ?

[spam3]

Posted on May 17, 2011 at 13:29

Hi everybody,

Is there a known issue with the DMA transfers between the ethernet MAC and the main memory while the processor is stopped with the WFI instruction?

In my code there is a handler for MAC interrupts that checks the DMASR bits and acknowledges them. In the meantime the main loop does WFI, and on wake up it checks the DMA descriptors for received packets. While all status bits seem to report a successful packet reception, the DMA buffer where the packet should have been copied is empty.

Now, if i remove the WFI instruction, and instead let the main loop constantly poll the DMA descriptors for OWN bits, everything works fine and the ethernet frame is copied to the DMA buffer.

I am wondering if the WFI instruction is preventing the DMA controller from accessing the memory. If that is so, is there a workaround? I am writing a real-time application and therefore the idea of constantly polling a chain of descriptors is not very attractive.

I have a STM32F107 chip, LQFP64. I don't know the exact revision but i can provide if it is required.

Any help would be greatly appreciated!

Regards,

--

Mat

[js23]

Posted on May 17, 2011 at 13:29

One additional note: I just changed the code of the lwIP Demo (AN3102)to completly interrupt driven with empty main loop. It is running fine as long as the loop is permanently executed. But as soon as a WFI is put into the loop, nothing is working anymore.

So I am quite sure now that the ethernet DMA stops when WFI puts the CPU in sleep mode. Is there any known workaround for this? I tried restarting the DMA by writing to DMARPDR with no success.

Energy consumption should be as low as possible for my app and it seems that I have to waste some 20mA...

[js23]

Posted on May 17, 2011 at 13:29

Just wanted to post exactly the same issue, but I did a quick forum search and found this post.

Did you find a solution for that in the meantime?

BTW: I use STM32F107VCT6 revision Z with date code 023

[js23]

Posted on May 17, 2011 at 13:29

Marcel, thank you very much for your reply.

I checked what you suggessted, but the value after reset for AHBENR is 0x14, so the SRAMEN bit is already set.

But you pointed me in the right direction: I played with some other bits and it seems that the DMA2EN needs to be set... (??!!)

The solution for the problem is now (for reasons I do not understand) simply calling:

RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE);

Regards,

Johannes

[mn2]

Posted on May 17, 2011 at 13:29

Hi,

After reset SRAM is disabled during sleep mode. You must set SRAMEN (bit 2/RCC_AHBPeriph_SRAM) in RCC_AHBENRegister.