Connecting STM32F7 FMC with SDRAM and 8 bit data bus

[MPatt.11]

When using a 16 bit data bus, the STM32CubeMX generates outputs for FMC_NBL1 and FMC_NBL0 that connect to the SDRAM DQMH and DQML pins. If the STM32CubeMX is configured for an 8 bit data bus, there is no DQM pin generated, although the 8 bit SDRAM has a DQM pin that needs to be connected somewhere.

I've searched the Reference Manual, Data Sheet and nowhere do I find what to do with the DQM pin in 8 bit mode. The SDRAM manufacturer has not been able to help answer this issue.

Has anyone run this configuration and can tell me where to connect the DQM pin on the SDRAM?

Thank you!

[Tesla DeLorean]

The performance here is going to be awful... If you are doing video it is likely to be a serious problem.

I'd half expect the FMC_NBL0 to decode appropriately, or you could use FMC_SDNE as the SDRAM pin is typically a don't-care on reads as best I can interpret the specs.

I'd recommend you talk it through with the FAE assigned to your account, and at the very least misconfigure a DISCO/EVAL board and probe the signals with a logic analyzer, and determine if you can work with the drag on the bandwidth.

[MPatt.11]

Thanks Clive,

I finally got a response from ST support, and they said to tie the DQM pins low at the SDRAM for 8 bit DRAM devices, and if I need UART8 which uses the FMC_NBL1 and FMC_NBL0 pins , then I can tie both DQM pins low on the DRAM when using a 16 bit device. There is no 8 bit access if you do that, read and write need to be 16 bits.

ST REALLY needs an app note on this. None of this covered anywhere.

[MEdgerton]

So to clarify if using a 16bit Data SDRAM (and Data in cubeIDE is set to 16 bit), you do not have to enable "16-bit byte enable" (its not clear its use and the infor buton dosnt help. Then on the DRAM tie both DQM lines low? This is only for DRAM wih 16bi data lines.

Following on: My 16bit data line DRAM has the DQM lines so if I enable the "16-bit byte enable" and use the lines does it mean it can use 16 bits and 8bi byte data?

The use cases aren't totaly clear.

[THoep.924]

Do not tie both DQM signals low! If you're using 8-bit data, you NEED to control DQML and tie it to NBL0. This had caused us days of frustration and debugging for our application as we took the advice of tying both of these signals low. The SDRAM datasheets will also say that this signal is required in order to avoid I/O bus contention when a read gets cancelled by a write. For the higher order byte (DQMH), and assuming you have those data lines pulled-down with resistors, the DQMH can be pulled-down.

[AShch.2]

Could ST engineers please confirm if it's OK to ground 8-bit SDRAM DQM pin?

[THoep.924]

@AShch.2​ Read my reply. We tried grounding in our initial design. The SDRAM seemed to work except it was causing very erratic behavior. You need to tie DQML with NBL0 on the SDRAM controller for proper operation.