Clock setup problem

[aoleon]

Posted on July 12, 2010 at 11:31

Clock setup problem

[daviddavid940]

Posted on May 17, 2011 at 13:58

Hi Alex,

Just before I try this on my board, sorry to ask a daft question but do you have STM32F10X_CL defined?

Martin.

[aoleon]

Posted on May 17, 2011 at 13:58

I found the problem!

When using PREDIV1 as a divider by 2 you have to write in two different registers (CFGR and CFGR2).

I've basicaly replaced RCC_CFGR_PLLXTPRE_PREDIV1by RCC_CFGR_PLLXTPRE_PREDIV1_Div2  (RM0008 Rev 11 page 144 explains why)

[code]

#ifdef STM32F10X_CL

    /* Configure PLLs ------------------------------------------------------*/

    /* PLL2 configuration: PLL2CLK = (HSE / 4) * 8 = 32 MHz */

    /* PREDIV1 configuration: PREDIV1CLK = HSE / 2 = 8 MHz */

        

    RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL |

                              RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC);

    RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV2 | RCC_CFGR2_PLL2MUL8 |

                             RCC_CFGR2_PREDIV1SRC_HSE | RCC_CFGR2_PREDIV1_DIV2);

  

    /* Enable PLL2 */

    RCC->CR |= RCC_CR_PLL2ON;

    /* Wait till PLL2 is ready */

    while((RCC->CR & RCC_CR_PLL2RDY) == 0)

    {

    }

    

   

    /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ 

    RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL);

    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLXTPRE_PREDIV1_Div2 | RCC_CFGR_PLLSRC_PREDIV1 | 

                            RCC_CFGR_PLLMULL9); 

#else    

[/code]

Alex

[aoleon]

Posted on May 17, 2011 at 13:58

Hello,

Thanks for those answers, STM32F10X_CL is defined as well as USE_STDPERIPH_DRIVER.

I've tried to recompile the entire project and still have the same problem ....

Alex

[domen23]

Posted on May 17, 2011 at 13:58

You might need to recompile FWLib... at least it was necessary on some older versions when changing HSE_Value.

[daviddavid940]

Posted on May 17, 2011 at 13:58

Hi Alex,

Cool.

Keil simulator was showing HCLK @ 144MHz. I personally prefer using the ST library calls and setting up manually like on the 103.

Cheers,

Martin.