Calibration issue on STM32H750 - DIV256 versus DIV1

[guys_fr]

The calibration at a DIV256 works most of the time but some MCU must be calibrated with a DIV1 otherwhise I get an offset of zero. We use VREFBUFF as reference. We try to swap an MCU with good result (DIV256 worked). One MCU calibrated but with errornous value, at least better at DIV1. Any ideas ?

ClockPrescaler = ADC_CLOCK_ASYNC_DIV1

HAL_ADC_Init(&hadc3)

HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED)

ClockPrescaler = ADC_CLOCK_ASYNC_DIV256;

HAL_ADC_Init(&hadc3)

HAL_ADCEx_Calibration_Start(&hadc3, ADC_CALIB_OFFSET, ADC_SINGLE_ENDED)

[FBL]

Hello @guys_fr​,

Could you please specify the revision of the part number STM32H750?

If the revision is V make sure that ADC kernel clock must be twice the frequency needed for the sampling as described in AN5312 section 1.7.1 ADC clocks.

[guys_fr]

The part number is STM32H750IBT6 - VQ116361 - AA078

PeriphClkInitStruct.PLL2.PLL2P = 120; // ADC: 12 = 20MHz, 80 = 3MHz, 120:2MHz, 128 Max

PeriphClkInitStruct.AdcClockSelection = RCC_ADCCLKSOURCE_PLL2;

I calibrate with a high prescaler to get "consistent" value between start-up. From AN5312, the DIV shall not be "one" but al least DIV2 and over.

Is this the expectation ?

1.7.1 ADC clocks

On RevV the ADC kernel clock must be twice the frequency needed for the sampling (as an example, if a 25 MHz clock is needed, ADC kernel clock must be set to 50 MHz).

My issue is that I get calibration value of zero if not using DIV1 with some MCU. We are looking into placing CAP really closer to MCU pin witch improve and an external Vref (stock issue here...).

ulCalibAtDiv1 = MX_ADC3_GetCalibValue();

To start, I do calibration with DIV1, DIV256 then check resulting value to choose from (zero not zero)

[guys_fr]

I think DIV256 is out of spec for low freq according to MX tools configuration, it shall be limited to DIV32.

[guys_fr]

Hello, Looking at the ADC3_Init closely, immediately following the LL_ADC_EnableInternalRegulator, I test the LDORDY (Mask/Rev "V") and rather then break the wait loop, I "idle the counter (wait_loop_index++) until it get true. Now, DIV1 calibration is stable and repeatable. Its some sort of 20% additionnal delay!