Cache problem with FreeRTOS and MPU

[JLima]

Hello everyone,

For my current project I need the FreeRTOS+MPU to work on H7. I got it somehow to work with DTCMs. However, when I try to move the complete memory allocation to the AXI SRAMs the FreeRTOS is hanging in the systick handler (there is a for(;;) there and goes out with break instructions).

After some experiments it was found that the system works if I do the following:

• Disable the DCACHE completly or
• Set an MPU region for the freeRTOS heap memory as non-cacheable (TEX = 001b, c = 0b, b = 0b)

I dont understand how I can have a cache coehrency problem since I dont have any DMAs or other processes writing into the AXI ram. The project is very very simple. It is just one thread and in the run function I have a counter incrementing.

To map the FreeRTOS to H7 I follow the steps on the following thread:

https://freertos.org/FreeRTOS_Support_Forum_Archive/May_2018/freertos_Cortex-M7_MPU_a9b4e3d5j.html

I attach the Attolic project here. in the main.h there are two compile switches. The system works if the ENABLE_DCACHE is commented or both ENABLE_DCACHE and ENABLE_NON_CACHEABLE_FREERTOS_HEAP are enabled.

I am running out of ideas what to try. Any help would be great.

I am using a Nucleo board in the project

THanks a lot,

Best regards,

Joao

[JLima]

​Just tried with an STMF7 nucleo board the exactly same example and putting the data in the SRAM1 and it works...It looks to be really H7 specific...

[JLima]

Still stuck with this issue..Anyone from ST that could take a look? What can I still try from the firmware perspective? Since it works with F7, I could imagine is either some difference to the H7 that I am not aware or maybe an HW bug.

[JLima]

My H7 board has the r1p1 and F7 the r1p0. So I guess the H7 board is even newer. Was there any changes in terms of cache management between these two revisions???

[JLima]

Could someone from ST please reply? This is currently a major blocking problem in my current project