bit-banding GPIO->ODR not possible?

[g239955]

Posted on September 26, 2014 at 10:46

Hello everyone,

since I'm toggling quite often some outputs, I try to access them via bit-banding. Unfortunately I can not access the GPIOs. I tested bit-banding for SRAMand RCC configuration without any problems. First of all, lets have a look atthe code snippet:

// prepare bit-banding 

#define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< 
Peripheral
base address in the bit-band region */ 

#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */ 


#define BITBAND_PERIPH(address, bit) ((__IO uint32_t *)(PERIPH_BB_BASE + (((uint32_t)address) - PERIPH_BASE) * 32 + (bit) * 4)) 

typedef volatile uint32_t * const bitband_t; 


// activate clk 

RCC->AHBENR |= RCC_AHBENR_GPIOAEN; 


// init two GPIOs 

GPIOA->MODER |= GPIO_MODER_MODER0_0 + GPIO_MODER_MODER1_0; 

GPIOA->OTYPER &= ~(GPIO_OTYPER_OT_0 + GPIO_OTYPER_OT_1); 

GPIOA->OSPEEDR |= GPIO_OSPEEDER_OSPEEDR0_0 + GPIO_OSPEEDER_OSPEEDR1_0; 

GPIOA->PUPDR &= ~(GPIO_PUPDR_PUPDR0 + GPIO_PUPDR_PUPDR1); 


// Set pin1 

GPIOA->ODR |= GPIO_ODR_1; 

// set pin 0 using bit-banding 

bitband_t gpioa_pin0 = BITBAND_PERIPH(&GPIOA->ODR, 0); 

*gpioa_pin0 = 1;

That's not the whole code, but the interesting steps. Line 2 and 3 are from stm32f30x.h Setting pin1 is no big deal,but setting pin0 doesn't. When building the alias address for the GPIOA->ODR register I realise an overflow. here my calculation for the final address (according toline4): The address of GPIOA->ODR is 0x48000 Minus the

PERIPH_BASE

remains 0x08000 Multiplied by 32 leads to an overflow 0x00000280 remains Adding

PERIPH_BB_BASE

and

bit*4

results in the final address is 0x42000 I've no idea which bit I'm manipulating, but that's not part of GPIOA. Is there any mistake? does anyone know how to access the GPIO? I'm working on a stm32f303cbt, using IAR Workbench. Thanks for your help! Gregor #gpio #stm32f303 #bit-banding

[waclawek.jan]

Posted on September 26, 2014 at 10:59

Generally, using bit-banding is not necessarily a faster option. You should benchmark and thoroughly study the available documentation.

Particularly not for GPIO, where the BSRR register provides the atomic read-modify-write facility through hardware.

GPIO in 'F3 is not in bit-bandable area. Read PM0214 chapter 2.2.5.

JW

[g239955]

Posted on September 26, 2014 at 11:19

Thanks for the answer!

I did read that I can access every register via aliasing...

sure, what's fast and what's not, I can't tell you at present. I'm just about familiarise myself with the uC.

[waclawek.jan]

Posted on September 26, 2014 at 11:22

> I did read that I can access every register via aliasing...

Where?

[Tesla DeLorean]

Posted on September 26, 2014 at 13:52

> I did read that I can access every register via aliasing...

 

Where?

Probably on other STM32, and Cortex-Mx blurb generally.

The problem is Bit-Banding has a limited range, 1MB as I recall. It doesn't support CCM at 0x10000000. And it's generally dangerous on peripherals, especially ones where RMW is eschewed in the design, like clear-on-write TIM->SR where RMW causes a race hazard.

The GPIO has specific support of set/clear individual bits in a single atomic write, so using a RMW is slow and wasteful, especially in designs with slower APB interfaces.