STM32 MCUs Embedded software

Hi everyone,I'm working on an STM32H743-based product that already has a custom bootloader and I'm looking for the best industry practice for implementing a bootloader fallback mechanism.Current architecture0x08000000 Primary Bootloader0x08020000 Factory Application0x08080000 Default ApplicationThe bootloader already performs:Application validity checks (MSP and Reset Handler) CRC verification of the Factory and Default applications UART firmware update Automatic fallback from Default Application to Factory ApplicationThe applications are working as expected.New requirementThe new requirement is that if the primary bootloader becomes corrupted, the system should be able to boot from a backup bootloader stored elsewhere in flash, without requiring physical access (the device is remotely deployed).I understand that after reset the Cortex-M7 hardware simply does:MSP = *(0x08000000)PC = *(0x08000004)and immediately jumps to the Reset_Handler.My understanding is:If the vector table or R

I’m using a Raspberry Pi host to flash an STM32G030 via I2C.The Raspberry Pi (all models except 5 and newer) have a known hardware bug in their I2C clock-stretching support.See e.g. https://www.advamation.com/knowhow/raspberrypi/rpi-i2c-bug.htmlThe interaction between a Raspberry Pi and the STM32 Bootloader over I2C is thus erratic. It works most of the time (including full verify, erase and flash cycles), but around 10% of the time, it will fail on the first two commands sent. Since it is quite timing-sensitive, with the bug triggering if the STM32 responds within a specific time window, that might be a reason why commands like GET, GET_VERSION, and GET_ID seem to be affected more, but flashing (which is sent much more often) works. Obviously there is little that can be done on the STM32 side. But I wish the AN4221 would document the followup behaviour of the Bootloader more clearly to help identify this issue.Notably, the STM32 gets into an invalid state, in which it does not respond

Hi there !I have a quick question about where the data are save. If i create one const array [1024] the data inside the array (because i write the word const in front) are save inside the falsh ? and this give to me more space in the ram  right ? and is the same if i create one struct and i acces with pointer ?  and please some one can help me and show where i can find all this kind of information like book tutorial website youtube ectThank you Sergio

I am trying to establish communication between an STM32F446ZCH6 and a LAN9253 using the Quad SPI (QSPI) interface on our custom hardware.As an initial validation, I am attempting to read the following LAN9253 registers: BYTE_TEST register (0x64) ID_REV (Chip ID) register (0x50) However, I am not receive the expected register values. Instead, the values returned are consistently 0x88888888 or 0xFFFFFFFF.To troubleshoot the issue, I captured the SPI/QSPI communication using a logic analyzer. From the waveforms, it appears that: The STM32 (master) is transmitting the read command correctly. The clock (SCK) and chip select (CS) signals appear normal. However, the LAN9253 does not respond with valid data, and the STM32 does not receive any meaningful data from the slave. We also attempted communication using: Single SPI (1-bit mode) Dual SPI (2-bit mode) Quad SPI (4-bit mode) Unfortunately, the behavior is the same in all three modes, with no valid response from the LAN9253.We hav

Struggling with a really weird issue here. I'm working on a project using Zephyr on an STM32U5A5ZJT6Q. We are using an LSE-clocked LPTIM as the tick source, PM enabled with STOP0 and STOP1 modes.At some point, we started noticing random crashes, which seemed to occur sporadically, more often on some boards than others. These would usually be in the `idle` zephyr thread, specifically after a `wfi` instruction. Digging around, I found some errata (specifically 2.2.26 for STM32U575xx STM32U585xx, related to flash prefetch, and now also 2.2.6 for STM32U59xxx STM32U5Axxx, related to wake-up from stop mode). HardFault on wake-up from Stop mode may occur in debug modeDescriptionA HardFault may occur at wake-up from Stop mode when the following conditions are met:• Device is in debug mode.• DBG_STOP bit is set in DBGMCU_CR.• A wake-up event/interrupt from an SRD peripheral (except EXTI) occurs in a timing window of four clockcycles during Stop mode entry sequence. SRD peripherals are

Hello,I downloaded STM32CubeN6-main FW 1.4.0 from GitHub and am trying to build the Nx_WebServer FSBL example.  I am getting this error message:11:26:53 **** Build of configuration Debug for project Nx_WebServer_FSBL ****make -j16 all make: *** No rule to make target 'C:/STM_FW/STM32CubeN6-main/Middlewares/ST/threadx/common/src/tx_block_pool_performance_info_get.c', needed by 'Middlewares/threadx/Performance/tx_block_pool_performance_info_get.o'. Stop."make -j16 all" terminated with exit code 2. Build might be incomplete.11:26:55 Build Failed. 1 errors, 0 warnings. (took 2s.214ms)I don’t see any source code at the C:\STM_FW\STM32CubeN6-main\Middlewares\ST\threadx location, is there another project I need to build first?

Hi,I'm developing a composite USB device on STM32N6 with:- 2x CDC ACM interfaces (Dual Virtual COM Port)- 1x UVC (USB Video Class) interface for camera streamingThe CDC ports work correctly. The UVC class enumerates successfully and the camera application opens without errors. However, the video stream shows a black screen - no actual frame datais being transmitted. What Works1. USB Composite device enumeration succeeds2. Both CDC ACM ports work (LOG port sends heartbeat, DATA port echoes)3. UVC class registers correctly with USBX4. Host can open camera application (VLC, Cheese, etc.)5. UVC GET_DEF(PROBE) requests are handled correctly6. SET_CUR(PROBE/COMMIT) requests are handled correctly7. StreamChange callback fires when host starts streaming (alt=1)8. Packets are queued via ux_device_class_video_write_payload_get() (returns success)9. ux_device_class_video_transmission_start() returns UX_SUCCESSWhat Doesn't Work→ PayloadDone callback is never triggered→ No video data reaches the ho

Setup  - MCU: STM32U595VITxQ (Cortex-M33)  - ADC: ADC4, 57Mhz，12-bit, 7 channels, 6400 Hz sample rate, triggered by TIM1  - Data path: GPDMA1 in linked-list circular mode, double-buffered with half/complete callbacks (128 samples per half-buffer). DMA writes directly into a static INT16U s_adc4_result[256][7] buffer in normal SRAM.  - Signal chain: external current/voltage sensors → signal conditioning board (op-amps, anti-alias filter, DC bias) → ADC4 input pins  - Firmware: FreeRTOS, half-callback copies 128 samples per channel into a ring buffer (PF_TOTAL_WAVE_NUM = 40 slots × 128 samples), pf_task consumes from queue  Symptom  Most of time, everything works fine. But some times something wrong happened，in a log file we captured, channels simultaneously read byte-identical constant values.Questions:  1. Has anyone seen an STM32U5 ADC report "healthy" (no OVR, no error, ADSTART set) while consistently delivering a constant code per channel? Are there silicon errata I should check?  2

 I’m trying to use the FMC and SDRAM (IS42S16400J) to expand the H7’s running memory. I have the FMC configured in SystemInit and the linker setup to put all readwrite into SDRAM. I’ve verified that I can create variables normally, they’re placed in SDRAM, and can be read and manipulated normally.Now that I have minimal functionality, I’m starting to add more peripherals and functionality.int main(void){ /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); /* USER CODE BEGIN Init */ /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); MX_SDMMC2_SD_Init(); MX_USB_OTG_HS_PCD_Init(); MX_FATFS_Init(); /* USER CODE BEGIN 2 */ MX_USB_DEVICE_Init(); /* USER CODE END 2 *

Hi everyone,I am working with the STM32C071 and experiencing problems with USB enumeration after my bootloader execution.I wrote a custom bootloader that performs checks (like CRC, metadata, etc.) and can also trigger the embedded STM32 DFU bootloader in System Memory using this method:void boot_jump_to_bootloader(void){ uint32_t i = 0; void (*SysMemBootJump)(void); uint32_t BootAddrC0 = 0x1FFF0000; __disable_irq(); SysTick->CTRL = 0; HAL_RCC_DeInit(); for (i = 0; i < 8; i++) { if (i < (sizeof(NVIC->ICER) / sizeof(NVIC->ICER[0]))) { NVIC->ICER[i] = 0xFFFFFFFF; NVIC->ICPR[i] = 0xFFFFFFFF; } } __enable_irq(); SysMemBootJump = (void (*)(void)) (*((uint32_t*) ((BootAddrC0 + 4)))); __set_MSP(*(uint32_t*) BootAddrC0); SysMemBootJump(); while (1) { /* Code should never reach this loop */ }}After performing my bootloader-specific instructions, I jump to the main firmware application using this f

After I configure EP1 to the double‑buffered mode, debugging reveals an issue inside stm32g4xx_hal_pcd.c. At line 1761, the endpoint register value is read. After executing PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); to clear the interrupt flag, the actual register content has already been updated. However at line‑1906, (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); still receives the register value captured before interrupt‑flag clearing. This triggers incorrect conditional judgements inside the HAL_PCD_EP_DB_Transmit() function.Probable root‑cause: When transmitting data for the first time under double‑buffered setup, USB_EPStartXfer populates both buffers by default. After Buffer‑0 finishes transmission and triggers an interrupt, the program reads register data at line‑1761 of stm32g4xx_hal_pcd.c. Right after this read operation, Buffer‑1 also completes its transmission and updates the endpoint register. Since HAL_PCD_EP_DB_Transmit uses the stale register value obtained earli

There seems to be a recurring error in the HAL documentation (e.g. UM2570, but also in others  STM32L5?) UM2570 - Rev 2 page 60/2926The description of the flag does not match the flag nameHAL_FDCAN_ERROR_FIFO_EMPTYPut element in full FIFOHAL_FDCAN_ERROR_FIFO_FULLGet element from empty FIFO 

Hello, everyone on the forum.I'm building a system using the STM32H735G-DK, ThreadX, and NetX Duo.I'm writing logs to a microSD card to keep a record of the system's operation.I integrated FTP into the system so that log files can be downloaded via Ethernet.Since the FTP download speed is only about 150 kilobytes per second, it takes a long time to download large log files.Currently, `nx_ftp_server_create` allocates an 8K-byte stack for the FTP server. What are some ways to increase FTP download speeds?I would appreciate any advice. 

My problem: my SPI2 module doesn’t appear to be clocking in data even if it is configured a full duplex master.Context:I am developing the firmware on a board that some other team designed and they picked PB13 (SCK), PB14 (MISO) and PB15 (MOSI) to implement SPI2.  I am aware of the fact that those pins are shared with the UCPD dead battery detection feature and that:Dead battery detection must be disabled Clock rate of SPI is limited to ~3MBdI am developing my drivers bare-metal (no LL or HAL), but since I couldn’t figure out how to make this work, I decided to try with the HAL code generated by STM32CubeMX.I created a new project on that software with software package v1.7.0 which appears to be the latest at this time.I simply configured the clock tree to use HSI (64MHz) → /2 → PLL1 (M=4, N=24, Q=4) = 48MHz.  I then use SPI2 prescaler to get 1.5Mbd out of PLL1Q (I tried lower data rate too).  The SPI module is configured in full duplex.  Here is the main function code after HAL initia

My MCU is STM32H753 on custom PCB. It is running at 480 Mhz. I use USB USB_OTG_FS it is clocked by RC48.On “Middleware and Software packs” I have enabled “FATFS”, “FREERTOS” and “USB_HOST”I generated project by using CubeMX 6.17 with “STM32Cube_FW_H7_V1.13.0”.For more details see attached pictures with configurations. I use FreeRTOS function uxTaskGetSystemState to get info about CPU time per task.In my project I have FatFS test module that performs some read write tests. When I check CPU usage I get this numbers for tasks: “fatfs_test” CPU: 43% “USBH_Queue” CPU: 46% left 11% are utilized by GUI.I ran tests with USB DMA enabled and disabled - there is no difference. So, the question is: Is it OK for “USBH_Queue” task to utilize that much CPU when read/write operations in progress??? For example I have similar test for SD-card, and I get this numbers for tasks: “fatfs_test” CPU: 51% “IDLE” CPU: 35% GUI and other tasks CPU: 14%USB OTG FS pinsUSB OTG FS parametersUSB OTG FS NVIC SettingsU

Hello,I am making a device which will play encoded audio files from a (Q)SPI flash and I wanted to use the STM32C55 (with its internal DAC). Alas, I haven’t been able to find flash/RAM/CPU frequency requirements for the codecs except for MP3 Helix (https://github.com/liuduanfei/helix), but I would rather use Opus because it has a better bitrate-to-quality ratio.Does anyone have experience with decoding audio on the STM32C55 (or any similar MCU for that matter)? How much flash and RAM was needed for the decoder?Thanks.

 I have activated spread spectrum on two of the three PLLs I’m using in an STM32H7S7 via codeLL_PLL_SpreadSpectrumTypeDef sspr2;LL_PLL_SpreadSpectrumTypeDef sspr3;// in SystemClock_Config LL_RCC_PLL2_EnableSpreadSpectrum(); LL_RCC_PLL3_EnableSpreadSpectrum(); sspr2.DitheringRPDFN = 1; sspr2.DitheringTPDFN = 0; sspr2.IncrementStep = 1200; sspr2.ModulationPeriod = 10; sspr2.SpreadMode = LL_RCC_PLL_SPREAD_CENTER; LL_RCC_PLL2_ConfigSpreadSpectrum(&sspr2); sspr3.DitheringRPDFN = 0; sspr3.DitheringTPDFN = 0; sspr3.IncrementStep = 214; sspr3.ModulationPeriod = 60; sspr3.SpreadMode = LL_RCC_PLL_SPREAD_CENTER; LL_RCC_PLL3_ConfigSpreadSpectrum(&sspr3);Is there a way in CubeMX to activate it to make the settings generated automatically, as everything else I’m using?I’ve checked the RCC section in System Core as well as the Clock Configuration tab, but I can’t see anything regarding spread spectrum

Hi everyone, I am facing an long-standing issue with a STM32L476RE-powered device loosing UART frames when waking up from UART3 from Stop Mode (will be analyzed on another issue).Prompted by this, I have a generic question for clock configuration after Stop1-2 mode.The device uses HSI & LSE for all of its peripherals, in a bare-metal CubeMX project.Q1: The function __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_HSI);is called 1 time before while(1){} loop. Should it be called just once or should it be called every time before calling HAL_SuspendTick();HAL_PWREx_EnterSTOP1Mode(PWR_STOPENTRY_WFI);?Q2: Should we call SystemClock_Config();every time after waking up from Stop mode, despite the fact that the clock selection ( HSI & LSE ) remains the same and no PLL or MSI is used ?Q3: Could calling SystemClock_Config();HAL_ResumeTick();disrupt an ongoing UART-RX ( running on Idle-line callback ) , despite the fact that clock selection is not changing ? Thank you in advance

Hi experts:    I’m working on NUCLEO-G031K8 trying to use its I2C2(I2C1 is OK),I set PA11/PA12 as SCL/SDA, pull-up, OD, when I tried to read data, I found SCL is always high, but SDA has datas, I can’t figure out what’s missing, can you help me with that?Bill 

Hello, I wrote a code to erase BANK2 flash memory for STM32G0C1VET6. The thing is that in some cases the erasing part works but in some cases it fails.I wrote the code to be ran in BANK1,the production code will use the proper start address and size, for this testing I’m forcing the erasing to happen in BANK2 for pages 0 and 1. As I commented, in some cases the erasing works, but sometimes there is an error returned by HAL_FLASHEx_Erase, which is HAL_TIMEOUT. I added proper refresh to watchdog and also some PREFETCH calls but even with that the issue persist. Attached is an image of the SR register once the HAL_TIMEOUT is returned. If I continue the execution of the code there is a hard fault caused when calling the HAL_FLASH_Lock (image attached). What could be wrong?I'm using STM32CubeIDE along with Stlink - V3.If the flash is already erased, calling the Erase function could cause the problem?Could it be related to some FLASH latency configurations?bool __attribute__((optimize("O0"))

UART independently working fine but with CAN, it is not working. Even simple welcome msg also no coming over UART . Even when I comment CAN init, issue is there. The error has been conveyed by a member earlier also. Any resolution provided by ST?

This is really a minor one. More an inconvenience than an actual problem. But it would be nice to get it solved, and to gain some understanding of what actually happens.I have a few different applications for various STM32 families, with a homemade bootloader added to it. The bootloaders are placed from address 0x08000000, and the applications begin at a higher address. Typically 0x08010000. The bootloaders and applications run fine. Bootloaders can start the applications, and applications can invoke the bootloaders. No problem there.The only issue I have is when uploading a new application from STM32CubeProgrammer, through the ST-LINK V3. I typically do this when debugging. But when I do it, even if the “Run after programming” checkbox is checked, the microcontroller isn’t started correctly after upload. When I debug this issue, the microcontroller seems to be stuck in an endless loop in the application. (Not the bootloader.)In the code I’m currently working on, this is the place wher

I have followed the instructions in GIT  to make ethernet works correctly on STM32H750 (setup TX/RX descriptors and their MPU config, also the LWIP heap and its MPU config, and the RX buffers).Everything seems working correctly after hours of setup and debugging, but the thing that break Ethernet and make it not working is when handling the unicast UDP or the UDP IO stream of OpEner it trigger a BUS Error in MAC DMA and stop everything from working, the explicit communication based on TCP works correctly and doesn’t break the Ethernet.I debugged for days of what could generate a bus fault error, then i find the udp when uses netconn it doesn’t copy the prepared buffer on lwip heap for sendig and in other way it give it directly the address of udp payload from the task stack, and this trigger a Bus Error when calling HAL_ETH_Transmit_IT because the task stack is not DMA accessible.So I made a workarround in low_level_output to detect the payload from outside lwip heap and copy that payl

Hello:Observation (empirical, multiple boundaries confirmed):When placing DMA linked list nodes (36 bytes each = 9 words) sequentially in SRAM1,if a single node spans certain addresses, the GPDMA channel enters DTEF statewhen fetching that node. Confirmed problematic boundaries in SRAM1 (192KB, 0x20000000 - 0x2002FFFF):- 0x20010000 : crossing FAILS- 0x20020000 : crossing FAILS Both boundaries appear at 64KB intervals within SRAM1, which suggeststhat SRAM1 may be internally organized as multiple 64KB blocks/banks. Test cases:Test 1: Node array starting at 0x20011A54 (natural placement)- Nodes 1-1633: within bank containing 0x20010000-0x2001FFFF → OK- Node 1634: spans 0x2001FFF8 - 0x2002001C → FAILS (crosses 0x20020000) Test 2: Node array starting at (0x20010000 - 44)- The first node spans 0x2000FFD4 - 0x2000FFF8 (OK)- The second node spans 0x2000FFF8 - 0x2001001C → FAILS (crosses 0x20010000) Test 3: Node array starting at (0x20010000 - 36)- The first node ends exactly at 0x20010000- No