STM32 MCUs Embedded software

Hello everyone,I measure a voltage on a STM32L496 using the internal ADC and found the following issue:Setup:The voltage is scaled down via a high-impedance voltage divider (2 x 470kOhm). To avoid distortion by sampling, the voltage divider has a 100nF capacitor. Thus, the capacitive load while sampling is low and the breakdown is 1/20000 → i.e. way lower than the ADC’s resolution. So I do not have to care about source impedance limitations as described in the datasheet (Maximum ADC RAIN).Other data:VREF=VDDA=3.3V (stable) Voltage range of ADC input signal: 0 - 3V (never >3.3V)Effect:I experience a large voltage breakdown when I configure the ADC, via CubeMX generated function MX_ADC3_Init (same happens when I use ADC1). I found, that within MX_ADC3_Init the channel gets configured and the ADC sequencer register ADC_SQR1 is set (I only sample that one channel with the high-impedance voltage divider). As soon as ADC_SQR1 is set, the voltage breaks down, from anything >2.5V to appr

In the topic “STM32U5G9J-DK2 application example \"Fx_NoR_Write_Read_File\" is not working” there is a problem described which I fear still is present today. The ticket mentioned there is 180260, can someone please check if the patch mentioned is available by now?Thanks.

I’m using an Infineon SEMPER NOR flash (JEDEC manufacturer ID 0x34; S28HS512T) with the STM32H7S78-DK XSPI2 interface. The bootloader uses STM32 External Memory Manager’s SFDP NOR driver, configured as EXTMEM_LINK_CONFIG_8LINES. The device has a hybrid sector map, and I’m updating mapped sectors from firmware stored on an SD card.The updater compares each logical sector, erases sectors marked for update, then writes the corresponding firmware data. Block-protection setup reports success: CLPEF (0x82), writes to CFR3V and STR1V (0x71), and a DYB unprotect write (0xE1) all return HAL_OK.For sector index 33, at address 0x00040000, size 262144 bytes, erase returns EXTMEM_OK (the measured duration was 0 ms). The subsequent write fails before any page-program command is sent: the driver’s initial WIP poll times out after 5 seconds.FW erase begin idx=33 logical=0x00040000 cmd=0x00040000 size=262144FW erase end idx=33 ... status=0 elapsed_ms=0FW write begin idx=33 addr=0x00040000 ... bytes=262

Subject: X-CUBE-CLASSB-L4 (STL) — Fault Injection Method for Flash/CPU/RAM Self-Tests on STM32L451CETI am applying X-CUBE-CLASSB-L4 (Self-Test Library, STL) on an STM32L451CET MCU to implement CPU/Flash/RAM self-tests for IEC 60730-1 Class B certification.Main issue: No matter what method I try, the Flash test never passes (always reports a failure / never completes successfully under normal conditions).Certification requirement: Our certification body requires us to demonstrate both the normal (pass) case and the fault (failure) case for each test, specifically by actually altering real values during test execution:CPU test: by actually changing register values during the test Flash test: by changing the CRC value, or modifying Flash memory contents while the test is running RAM test: by modifying RAM contents while the test is runningI understand that ST's recommended method is to use STL_ArtifFailingConfig to perform fault injection. However, this only simulates a failing configurat

Board / softwareSTM32N6570-DK (MB1939), STM32N657X0H3Q STM32Cube FW_N6 V1.4.1, ThreadX + USBX from the package (not X-CUBE) STM32CubeIDE, load-and-run development flow (ELF downloaded into internal SRAM by the debugger; no FSBL, no XIP, no external loader) USB2_OTG_HS configured as Host_HS on CN17, internal HS PHY OTGPHY2 clock = RCC_USBPHY2CLKSOURCE_HSE_DIRECT, 24 MHz HSE crystal CPU 600 MHz, AHB 200 MHz USBX: UX_MAX_DEVICES 8, UX_APP_MEM_POOL_SIZE 98304, USBX_MEMORY_STACK_SIZE 65536, only the CDC-ACM class registeredWhat worksA USB 2.0 mass-storage device (HP, VID 0x03F0 / PID 0x2003) enumerates reliably and repeatedly:[usb] idVendor : 0x03F0[usb] idProduct : 0x2003[usb] bcdUSB : 0x0210[usb] bMaxPacketSize0 : 64[usb] speed : HIGH[usb] state : ADDRESSED[usb] -- interface 0 class 0x08 (mass storage) 0x06/0x50[usb] ep 0x81 BULK IN mps 512[usb] ep 0x02 BULK OUT mps 512UX_DEVICE_ENUMERATION_FAILURE here is e

Hi,I'm working with an STM32N6570-DK and need the microSD slot (CN13, SDMMC2) to run at 1.8V signaling instead of the 3.3V default. The device I'm connecting only supports 1.8V, and the target speed is modest, around 25 MHz.What's the correct procedure to make this switch on this board?So far I've driven SD_SEL (PO5) high to flip U32, but CN13 pin 3 still measures 3.3V. AN5967 (Getting started with hardware development for STM32N6) section 12.4 points to PWR_SVMCR2.VDDIO5VRSEL together with OTP124 bit 13 (HSLV_VDDIO5), which currently reads 0 on my board.Two things I'm unsure about: Is burning HSLV_VDDIO5 actually required for 1.8V operation, or only to reach the datasheet frequencies?  Does burning it permanently prevent the slot from working with ordinary 3.3V SD cards?  

Main goal is to measure the RMS value of the mains, first question is can i perform the calculations using floating point or fixed point? The RMS requires the sqrtf function, can i use the function due to its number of cycles?

Hello STM32 Community,I am currently working on a USB Flash Drive interface using STM32G0B1RET6 with USB Host and FatFs.The USB Flash Drive is working correctly. When I plug in a USB Pendrive, my STM32 can detect it, mount the filesystem, and successfully create/write files to the Pendrive.Now I would like to display/check the following information:Total USB Flash Drive storage Used storage Free/available storage Detect whether the USB is almost fullMy current code is:static void USBH_UserProcess(USBH_HandleTypeDef *phost, uint8_t id){ switch (id) { case HOST_USER_CLASS_ACTIVE: Appli_state = APPLICATION_READY; USB_Detect_flag = 1; // USB is plugged Mount_USB(); HAL_GPIO_WritePin(GPIOC, LED_RED_Pin, GPIO_PIN_RESET); /* Check USB free space */ if (usb_space_result == FR_OK) { displayText16x16_DMA(20, 190, "USB HAS SPACE",

Hello,on a shared SPI bus (one master, several slaves, one NSS line per slave, the "Standard multislave communication" topology of RM0456 §68.4.5), an STM32U5 SPI slave with hardware NSS sometimes ends a transaction early. EOT is raised 112 or 126 bytes (frames) before TSIZE, with no UDR, OVR, MODF or FRE flag. The slave then stops driving MISO, so the master receives the last ~110 bytes as 0x00, while on the slave the HAL reports a normal "transfer complete". The data corruption is silent.When it happensEach slave prepares its next transfer on its own, with HAL_SPI_TransmitReceive_DMA, which sets SPE as its last step, and then raises a "ready" GPIO for the master. So the call sometimes falls while the master is clocking another slave: this slave's NSS is high and SCK is toggling. That is the only case in which the failure appears.With only one slave active (no foreign traffic on SCK) it never happens. It is the instant SPE is set that matters, not the DMA setup. Our workaround: prepar

Hello, I’m working of a TM32F769 board the content of the 4 KB backup SRAM (BKPSRAM,0x40024000) is lost after a hard power cycle (VDD removed and re-applied),although:  - VBAT is supplied by a 3 V lithium coin cell (Renata, CR1225-type),  - the backup regulator is enabled (PWR_CSR1.BRE = 1) and ready    (PWR_CSR1.BRR = 1) before power-off, and BRE is still set at the next    cold boot,  - the rest of the backup domain is retained: RCC_BDCR keeps its value    (LSE on/ready, RTCSEL = LSE, RTCEN = 1) and the RTC keeps running,  - HAL_PWREx_EnableBkUpReg() returns HAL_OK,  - BKPSRAM content IS retained across system resets (NRST / IWDG) while    VDD stays present. The test I have performed: 1. Flash and run the firmware once (writes 0xDEADBEEF to BKPSRAM word 0). 2. Disconnect the ST-LINK cable from the board (to avoid back-powering    through SWD pins). 3. Remove all board power (VDD). The coin cell stays connected to VBAT. 4. Wait for 5 min. 5. Power the board up without the debugger and

In RM0490 Rev 6, Reference Manual for the STM32C0, the ADC Software Calibration Process is specified as follows: Software calibration procedure1. Ensure that ADEN = 0, AUTOFF = 0, ADVREGEN = 1, and DMAEN = 0.2. Set ADCAL = 1.3. Wait until ADCAL = 0 (or until EOCAL = 1). This can be handled by interrupt if theinterrupt is enabled by setting the EOCALIE bit in the ADC_IER register.4. The calibration factor minus one can then be read from bits 6:0 of the ADC_DR orADC_CALFACT registers. The resulting calibration factor must be incremented by oneand written back to the ADC_CALFACT register.5. To reduce the noise effect of the calibration factor extraction, the software can makethe average of eight calibration factor values. This step is optional but recommendedfor better accuracy.The averaging procedure is as followsa) Obtain eight incremented calibration factor values (perform eight times step 2 tostep 4).b) Calculate the average of these eight values and round it up to the nearest integer

Hello everyone,I'm developing an application using the STM32H563 with TrustZone enabled. Online tutorials first show configuring the fuse bits using the STMCubeProgrammer software:TZENSECWM1_STRTSECWM1_ENDSECWM2_STRTSECWM2_ENDThen, the application is installed in the STMCubeIDE, where it is saved and executed correctly.However, if the developer tries to install the application without going through the first step, the code is unable to exit the safe zone, resulting in a hard fault error. This is because the IDE, when TrustZone is enabled, assumes that all FLASH memory is in the safe zone.I would like to change these fuse bits without using STMCubeProgrammer. I believe it's possible, but I haven't found any information where the result is satisfactory. Could someone help me?

Here is my main and jump to bootloader :int main(void){ HAL_Init(); SystemPower_Config(); SystemClock_Config(); HAL_Delay(500); // Catch bootloader constantly resetting jump_to_bootloader(); while (1) { HAL_Delay(50); }}#define BOOTLOADER_ADDR (0x0BF90000UL)HAL_StatusTypeDef jump_to_bootloader(void){ __disable_irq(); HAL_RCC_DeInit(); // Must be run before disabling systick because it depends on it HAL_DeInit(); SysTick->CTRL = 0U; // Disable systick SysTick->LOAD = 0U; SysTick->VAL = 0U; int count = sizeof(NVIC->ICER)/sizeof(NVIC->ICER[0]); for (int i = 0; i < count; i++) { // Clear pending interrupts NVIC->ICER[i]=0xFFFFFFFFUL; NVIC->ICPR[i]=0xFFFFFFFFUL; } void (*jump_to_bootloader_fptr)(void); jump_to_bootloader_fptr = (void (*)(void)) (*((uint32_t *) ((BOOTLOADER_ADDR + 4)))); __enable_irq(); __set_MSP(*(uint32_t *)BOOTLOADER_ADDR); jump_to_bootloader_fptr(); return HAL_ERROR; // Should never get there because of jump}

Hi, I am wondering if anyone has had any experience using the STM32N6 onboard H264 encoder? I am trying to write a business case for using this MCU, which claims it can broadcast H264 video at 720p & Audio at a stable 30fps over LAN without any noticeable drops in performance? The only solutions I have found so far have been dedicated SoC.

Hi all,I'm recording 16 kHz mono audio from the on-board digital MEMS mic (MP23DB01HP) of the STM32N6570-DK using the BSP's MDF path (MDF1, filter 0, PE2 MDF1_CCK0, PE8 MDF1_DATIN0, GPDMA1 channel 0, SPI mode, falling edge). The recording runs next to a camera/ISP pipeline, an NPU model and an H.264 encoder, so I want the audio path to cost as little CPU as possible and sound clean.Current setup (BSP defaults for 16 kHz)Kernel clock: IC8 from PLL4 = 50 MHz (HSI-based), PROCDIV = 2, CCKDIV = 12, so the PDM clock is about 2.08 MHz CIC: Sinc4, R = 32; reshape filter on, ÷4 (total decimation 128) Gain +2 (about +6 dB); HPF 0.000625 × fPCM (about 10 Hz) Async continuous acquisition, circular DMA into a 16 KB bufferWhat I triedI built a test firmware that records one clip per MDF configuration (5 s each, one config per boot) and compared them offline. Configs: Sinc4 vs Sinc5 R = 32 (gain steps −7, −8, −9), HPF at 10, 20, 40 and 152 Hz, a PLL4 retune to 81.92 MHz with IC8 ÷ 10 for an exact 2.

Hello ST Community,I am working with the STM32U535RET6 and need clarification on the interaction between the IWDG Window feature and Early Wake-up Interrupt (EWI).I tested the following configurations:1. Window enabled, EWI disabledThe Window feature works as expected:Early refresh → IWDG reset Late/no refresh → IWDG reset2. EWI enabled, Window disabledWhen only EWI is enabled, the EWI interrupt occurs when the counter reaches the configured EWIT value.In the ISR, the HAL code acknowledges the EWI by setting EWIC.According to RM0456, writing EWIC = 1 clears EWIF and also reloads the IWDG counter with RL[11:0].However, in my observation, the EWI ISR is called only once, and I do not observe the expected counter reload after the EWI acknowledgement.3. EWI and Window enabled togetherWhen both features are enabled, I observe different behavior.For example, with EWI configured for approximately 2 seconds, the EWI occurs repeatedly at approximately every 2 seconds. The IWDG counter appears t

This post is in response to the following post which has been closed so I am unable to reply...  Update – root cause found: STM32CubeProgrammer flash loader / FLASH_SR.PEMPTYI have finally found the cause of this issue and a reproducible workaround.The problem is related to the PEMPTY bit (bit 17) in FLASH_SR.On a failed debug/programming attempt I measured:FLASH_SR = 0x00020000 (PEMPTY = 1)SYSCFG->MEMRMP = 0x1SCB->VTOR = 0x1FFFF000PC = 0x1FFFxxxxThe MCU had therefore booted into System Memory rather than the application.On the next, successful attempt:FLASH_SR = 0x00000000 (PEMPTY = 0)SYSCFG->MEMRMP = 0x0PC = 0x0800xxxxThe option bytes were identical in both cases:FLASH->OPTR = 0xFFFF98AAI could reproduce this indefinitely: one programming attempt failed, the next worked, then failed, then worked.As a test, on a failed attempt I manually executed:set *(int*)0x40022010 = *(int*)0x40022010This changed FLASH_SR from:0x00020000to:0x00000000After subsequently resetting the

Dear forum,I am trying to setup a simple application to sample an ADC channel with DMA and stream it via UDP to a Windows PC, so here’s what I did:I started from the sample project “Nx_UDP_Echo_Client”, provided by ST in FW pack; I configured the ADC peripheral to sample pin PA1 as in the sample project “ADC_SingleConversion_TriggerTimer_DMA”, and this is ok; I configured the GPDMA channel 0 in circular mode to copy ADC.DR into a buffer, following this and this; I put the DMA buffer in a dedicated memory region (AHBSRAM1), as suggested here; I configured the buffer memory region as NON CACHEABLE in MPU configuration, as suggested here; Finally I configured the RISAF in order to let the GPDMA have access to the buffer, as suggested here.But still, when I try to activate the transfer with the HAL command HAL_ADC_Start_DMA, I get a “User setting error” (USEF bit in GPDMA_C0SR register) and the GPDMA channel is deactivated. Can you please help me in the debug?The project, which is attached

Hi forum,I’m tasked to implement firmware update ability for an STM32-based application. Basically, I’m using this tutorial and change it to work on a NUCLEO G431RB board. In the end, we’ll have a bootloader and two application slots in the STM’s flash.The situation now is this: Bootloader starts up, waits for a moment, checks for a condition (button pressed or not) and then transfers control to either application 0 or application 1. Both applications don’t do anything useful yet, they just differ in how they blink the one LED I’m able to manipulate easily.Startup works, transfer works but application 1 doesn’t blink at all. Reason is that its HAL_GetTick() value doesn’t change. In bootloader, it does. In application 0, it does also. And if I flash application 1 onto flash address 0x08000000 all alone without the other two, it works.And it also works if I change the marked line to initialize variable to zero.#define NumberOfFlashes 3static int _millisecondsUntilToggle = 5; // marked

Hi everyone, I have developed a custom pcb board and I want to use the usb and a uSD card. I am not really familiar with pcb designing. My guidance was some youtube videos in general, like the Phil’s Lab for the USB + SD MSC (The link, so there is some understanding on the code I have added to the usb app). The USB works. The SD only worked once somehow, while I was stepping the code in the debugging process. I could not do it again. I have tried every possible configuration. The only thing I get is the following from the terminal: [28067.786253] usb 3-4: new full-speed USB device number 86 using xhci_hcd[28067.913272] usb 3-4: New USB device found, idVendor=0483, idProduct=572a, bcdDevice= 2.00[28067.913281] usb 3-4: New USB device strings: Mfr=1, Product=2, SerialNumber=3[28067.913283] usb 3-4: Product: STM32 Mass Storage[28067.913286] usb 3-4: Manufacturer: STMicroelectronics[28067.913288] usb 3-4: SerialNumber: 395834673434[28067.916167] usb-storage 3-4:1.0: USB Mass Storage device

Hi everyone,I'm using UART Receive-to-IDLE with circular linked-list GPDMA on an STM32H7RS and ran into a problem where reception stopped with HAL_DMA_ERROR_DTE.The DMA node and RX buffer are both in DMA-accessible, non-cacheable RAM and aligned to 32 bytes.The DMA handle and queue structure are in normal BSS. Everything is global/static and zero-initialized.I checked the queue/node connection and the source address in LinkRegisters[3], which correctly pointed to UART RDR. The node address reconstructed from CLBAR and CLLR was also correct when checked.However, these were the actual DMA register values in the working and failing cases: Working FailingCBR1 0x00000080 0x0000049BCSAR 0x40007824 0x00000005CDAR 0x24001960 0x200065A0After the DMA error, UART error handling stopped reception and disabled the IDLE interrupt, so I stopped getting HAL_UARTEx_RxEventCallback() calls.What fixed it was adding __DSB() inside HAL_DMAEx_List_Start_IT(), after the CLB

Hello everyone,I am having an issue with EEPROM Emulation initialization in my STM32 project.I am currently trying to implement the EEPROM Emulation utility using STM32CubeMX2 v1.1.0.The program starts with mx_system_init(), which initializes the peripherals and other required modules such as FLASH, RCC, etc. After that, I call mx_eeprom_emulation_init(). During this initialization, the MCU enters a HardFault.Detailed informationThe call hierarchy is:main() → mx_eeprom_emulation_init() → EE_Init() → EE_FLITF_Init() → Page_GetState() → EE_ITF_FLASH_ReadData()Inside EE_ITF_FLASH_ReadData(), the code tries to access address:0x09000018and immediately enters a HardFault.I also analyzed the fault using the Fault Analyzer in STM32CubeProgrammer. The results are:SCB_BFAR: 0x09000018 BusFault: Precise data access error (PRECISERR) The BusFault is escalated to a HardFault (FORCED)I also checked the EDATA_EN option bit in STM32CubeProgrammer, and it appears to be enabled correctly.At this point,

This is the follow-up to my 2023 thread, which is now closed for replies:https://community.st.com/stm32cubeide-mcus-28/azurertos-netxduo-unable-to-download-16k-or-larger-image-using-web-http-client-secure-124990Short version: the stall is in the ST NetX Ethernet glue driver (`nx_stm32_eth_driver.c`), not in NetX Duo, and not a packet-pool sizing problem. The fix is about 40 lines and still applies to the current `STMicroelectronics/stm32-mw-netxduo` main branch, which has the same driver code. I have filed it with ST as a bug with the full write-up and patch: https://github.com/STMicroelectronics/stm32-mw-netxduo/issues/1 **Symptom (from the original thread)**HTTPS downloads of 16 KB or more via `nx_web_http_client` + NetX Secure stalled on every attempt on F417, F429 and H723. Plain HTTP downloaded multi-MB files fine with the same pool. After a stall the socket stayed ESTABLISHED and the pool showed fewer free packets than expected, which I wrongly reported as "free_packets corrupted

Background info:I am looking at ditching Microchip and moving to STM32 H5 or H7.My application requires networking and support for HTTP server, SNTP client, SNMP V2 & V3 agent and SMTP client with TLS etcI am looking at H5/H7 primarily because of the larger RAM to support a TFT display of 320x240 or possibly 480x320. I only need 16 bit color.  Now the question:I am evaluating my choices for a TCP/IP stack. The “free” contenders appear to be LWIP and Azure (NetX) and I have seen some not free offerings such as CyloneTCP and Mongoose.I suspect that any of them can be made to work with enough effort but in the interest of not wasting company resources I thought it prudent to see who has had successes and frustrations with the offerings that I have been exploring.Yes. I am the guy who asks how deep the water is before I jump in….