Power management

Dear all,I am making a SMPS to operate from PV voltage (35-120V) to 24V@1A . circuit is not working because VCC is not developing even though startup resistance is reduced. No VCC , there is no Vref = 5V and hence no opertation. I have attached my schematic as well pcb layout. Please share your feedback on layout as well. Thanks a lot 

Hello,I’m reviewing a design that uses an STM32F767ZIT6 as the I²C_3 master. This I2C_3 bus is shared by: U18: PCA9535A I/O expander U19: SHT40 temperature and humidity sensor U3: STUSB4500 USB-C PD sink controller SDA and SCL have external 2.2 kΩ pull-ups to 3.3 V. In the schematic, the STUSB4500’s VSYS pin (pin 22) is  connected to GND, and its VDD supply appears to come from the USB VBUS path. Therefore, when no USB-C cable is connected, I believe both VDD and VSYS may be absent.The STUSB4500 datasheet’s I²C pin description says that SCL and SDA are pulled down when neither VDD nor VSYS is present.Could you please confirm: With both VDD and VSYS absent, will the STUSB4500 pull SDA and SCL low strongly enough to prevent the STM32 from communicating with the other devices(U18, U19) on the shared bus? Is it acceptable to connect VSYS to the board’s 3.3 V rail so the STUSB4500 remains powered when USB-C is disconnected? Would this affect USB-C attach detection, VBUS monitoring, or

Have a quick question about the RHFL4913 regulator. Is the internal reference trimmed such that it is unlikely (or impossible) that the internal range would be at/near the min/max limits?i.e. not near the 1.19 or 1.27 limits? If it’s trimmed we would expect the reference to be within about 1 sigma from nominal. We are trying to understand the probability that the reference will be at or very near its endpoints. 

Dear Sir,We are evaluating the VN9E30F, a 6-channel automotive high-side driver with a 24-bit SPI interface. Kindly clarify whether the IC provides real-time switching status or feedback through a register that can be read via SPI.Also, please confirm the current availability and supply status of this IC.Thank you.

I am currently using the STGAP3SXS gate driver and would like to clarify the behavior of the DIAG pin when the RST input is driven low. I could not determine from the datasheet whether the DIAG output is directly affected by the state of RST.Could you please confirm the following?When RST is held low and no DESAT fault is present, what is the expected state of DIAG  Is DIAG asserted low only when a DESAT event has occurred?A brief timing description or state diagram of the interaction between RST, DIAG, RDY  and the DESAT latch would be greatly appreciated.Thank you for your support.Best regards, 

Hi,Can I drive the SGT1D5R10MEA with a normal bootstrap gate driver(standard silicon MOSFET drivers), one that has no regulated high-side supply? I could not find a clear answer in the data brief or in AN6268.My setup16S battery: 60.8 V nominal, 69.6 V maximum. 4-in-1 drone ESC, 20 kHz, 6-step sensorless control. One SGT1D5R10MEA per switch position. Driver: 3-phase half-bridge bootstrap driver with an external bootstrap diode and one gate supply (GVDD) of 5.4 V. Gate supply limit for the FET: VGS is 6 V maximum, as I read the datasheet.My questionsIs a standard bootstrap driver supported for this device, or does ST require a driver with a regulated high-side supply, such as the 6 V regulator in the STDRIVEG611? If standard drivers are allowed, what clamp does ST recommend? What is V_SD at 100 A and 200 A across temperature? I only see the 50 A value. Is there a tested reference design, or a list of recommended drivers for this part?Thank You.With regard,Kaviselvan.

Hi, I want to design a 600 W converter which should work during power shut down 190 V to 60 V input and output voltage will be 300 V. Switching frequency 150 kHz to 190 kHz. Want to use L6462A IC as there is a evel board which perform the same (ACDC  -- PN: EVL6462A-250W-M). Operation time = 100 msec.I also need an enable signal to turn on the DCDC converter.Please let me help to design the schematic and are we able to use L6462A IC for the application. Additional Information:Topology is already selected and simulation is done. --- Non isolated boost converter. L6462A is ok to use? ST already build an eval board as PFC. Can anyone provide me the schematics or suggestion for the DCDC converter. Peak current controller is fine. I also want to mention that we already build the dcdc converter with TI28379D microcontroller. Reason to use the IC (L6462A or else) because we want to bypass the software coding.

Dear Team, We are using the ST8R00WPUR boost converter to step up the input voltage from 5 V to 12 V in one of our designs.We would like to conduct a design review of the attached circuit. Please review the design and share your feedback/comments.Additionally, we noticed that the Junction-to-Board (θJB) thermal resistance data is not provided in the datasheet. We would appreciate it if you could share the Junction-to-Board thermal resistance value, as this information will be helpful for our thermal simulation and analysis. Best RegardsAbhishek

Hello,We are investigating a recurring failure of an L7983 used in a medical device.Application:VIN ≈ 40 V VOUT = 5 V L = 68 µH Cout = 2.2 µF LCM mode Very light load conditions possibleFailure mode:5 V output lost. After removing the output inductor, LX remains shorted to GND. Resistance LX-GND ≈ 2.5 Ω. High-side MOSFET appears intact (no abnormal resistance between VIN and LX). Failure seems limited to the internal low-side MOSFET.Field observations:The failure is always preceded by a battery-related error. Batteries are often found degraded or unable to charge correctly. Similar failures have also occurred during production.Tests performed:Startup without battery. Startup with low battery conditions. Long-duration operation with low battery voltage. Heavy battery discharge during operation. Various startup sequences.No test has reproduced the failure so far.Measurements:LX peak ≈ 50 V. Undershoot down to approximately -1.7V No obvious overcurrent event detected.Questions:Have you se

 1. Executive SummaryDuring evaluation of the vienna_stm32g474 reference project, a data-rate decoupling effect was identified in the main PFC voltage control loop. The physical DC-link voltage feedback structure (VOLTAGE_ADC_DC_IN_PHY) is calculated inside a 2 kHz telemetry task (TIM7), but it is consumed by the main cascaded controller (DPC_LCT_PFC_Ctrl) operating within the 20 kHz interrupt loop (TIM2).Although the raw ADC data is sampled at 20 kHz (TIM2) and is immediately available in the Data Layer via DPC_CDT_DcVoltageRead(), the conversion to physical units is delayed by the low-frequency task. This feedback latency was previously masked by a 16-bit register truncation error in TIM7, which forced its real execution frequency up to ~8.7 kHz. Testing confirms that relocating the physical voltage scale conversion (DPC_ADC_VoltageDCAdc2PhyProcessData) to the 8 kHz voltage loop task (TIM6) resolves this constraint, optimizing PI controller responsiveness and improving grid current w

Hi ST team,We received batches of BTB04-600SL triacs with two different body markings:Marked: BTB04-600SL Marked: BTB04600SL (no dash separator)Could you help confirm:Are they electrically identical, same die and specification? Is the dash "-" optional for component laser marking?Best regardsL Ma

I am evaluating the SM6F18AY TVS diode for a 12 V automotive ECU input-protection circuit.The SM6FxxAY datasheet (DS13062) states compliance with ISO 7637-2 Pulse 1, Pulse 2a, Pulse 3a and Pulse 3b.Could you please provide the detailed test report or characterization data for SM6F18AY, including:Test conditions for each ISO 7637-2 pulse, including source resistance and pulse duration. Number of pulses applied and interval between pulses. Initial battery voltage used during testing. Maximum clamping voltage observed during each test. Whether the testing was performed specifically on SM6F18AY or on a representative device from the SM6FY family. Confirmation of suitability for 500 repetitions of Pulse 1 and Pulse 2a, with a 5-second interval between pulses.Our application requires:Pulse 1: −150 V, 10 Ω, 2 ms, 500 pulses. Pulse 2a: +112 V, 2 Ω, 50 µs, 500 pulses. Pulse 3a: −220 V, 50 Ω, 150 ns. Pulse 3b: +150 V, 50 Ω, 150 ns.Thanks,Pradeep

Hello, I am designing the power supply section for my board.The connector on the left is intended to connect to a LiPo battery. My voltage regulators and the BQ2407 are arranged in a pyramid-like configuration: there are three LDOs beneath the BQ2407, and below those, two buck converters. I’m reaching out because the current layout doesn't look very aesthetic, and I’m struggling to find a way to make it appear more professional.Any advice would be greatly appreciated. Thanks! 

In trying to read the I2C registers of the STUSB4500, I find that the information provided in the combination of UM2473, UM2650, DS12499, and even STSW-STUSB033 to be incomplete and at time contradictory. For example STSW-STUSB003 references rev 2 of the document and the current revision is 3 and they don’t agree. Mush of what I find here on the community is 7 or 8 years old and of a very similar complaint.Is there one source that provides all of the data concisely? This is needed for a project where connecting to a NUCLEO-F072RB is not feasible.Thanks

I'm hoping to use the EVLSTGAP3SXS-H as a half-bridge converter for active charge balancing on a battery energy storage system, but I have a few questions about the data sheet provided in the products page.Bus voltage ratingThe data brief limits the high-voltage rail to 520 V "by the MOSFET's and capacitor's rating". However, the SCTWA70N120G2V-4 MOSFETs are rated for 1200 V and C4 is listed as 3.3 µF / 1.1 kV. The description also says the bus can be raised to 1200 V by replacing the MOSFETs and C4, which already appear to be 1200 V / 1.1 kV parts. What component or design limit actually sets the 520 V rating (for example PCB clearance/creepage, the R1/R2/R83 resistors, startup overshoot without precharge, or another part)? Can the board be operated at up to 700 V DC as supplied? If not, which parts would need to be changed?Output current and PCB copperWe need to run 10 A continuous (DC average, with ripple) through the HV, OUT and GND_PWR paths. What is the copper weight and minimum

Is there a recommended heat sink for EVLSTGAP3SXS-H? I would like to continuously run the device at 10 A but there are no heatsinks or clear thermal paths on the board. 

I’m using STEVAL-WBC2TX70 and needs STSW-WBC2STUDIO.However, the software is not available online.Can anyone send me the software ?

Hi I am using STUSB4500 using a usb c connector. The usb c connector is connected to XP power ac dc 65w adapter  capable of delivering 20V, upto 3.25A. STUSB4500 is never programmed over I2C and should have its default PDOs. By default settings I mean when it is connected to the XP charger, it should request by default 20V,1A from this source. Since its Req_src_current but is also 0 by default, so it should only demand 20W(20V,1A) from source even though source can deliver upto 3.25A. But I desoldered a 0 ohm resistor in the usb vbus path  after STUSB4500 and installed ammeter there and found out that 2A is flowing through vbus instead of 1A. Is this normal?As I see 20V is being delivered to load but the current is double than what’s requested. One thing worth mentioning is that load connected on the downstream path after STUSB4500 is capable of receiving upto 2.8A.but I don’t think load should have anything to say here and the STUSB4500 should request only its default 20V, 1A from PGW

Hello Community,I would like to report another significant logic bug in the generated firmware libraries for the Vienna Rectifier project (specifically located in the Digital Power Control stack file BSP/DPC_FW_PACK/src/DPC_Loopctrl.c).The Issue:Inside the function DPC_LCT_FeedForwardCtrl(..), the firmware is supposed to evaluate whether the AC Voltage Feed-Forward task is enabled before adding the d-axis and q-axis AC feed-forward grid terms (fVd_feed_sub and fVq_feed_sub) to the current loop outputs.However, the original ST framework code erroneously checks the DC voltage feed-forward enable flag instead of the AC one.The Code Snippet:cvoid DPC_LCT_FeedForwardCtrl(DPC_LCT_CDC_t *pCDC_sub, float *pVd_ctrl_FF_sub, float *pVq_ctrl_FF_sub){ float fVd_feed_sub = pCDC_sub->fVdFeed; float fVq_feed_sub = pCDC_sub->fVqFeed; float fVd_ctrl_sub = pCDC_sub->fVdCurrentCtrl; float fVq_ctrl_sub = pCDC_sub->fVqCurrentCtrl; /* AC feedforward task */ // BUG: Checks bVDC_FF_Enable

Hi,We are developing a 380W/400W electronic ballast for a Mercury UV lamp (Dymax 36970), based on the circuit topology presented in ST AN2747 – 250W HID Metal Halide Electronic Ballast.Lamp specifications: P/N: 36970 (Brand: DYMAX) Rated power: 380W Lamp voltage: 135V ±15V Lamp current: 3.2A AC input: 230V We would appreciate technical guidance on the following questions: Topology: Is the AN2747 circuit suitable for scaling from 250W to 380–400W for a Mercury UV lamp? Power stage: Which components and design calculations need to be revised, particularly the PFC, MOSFETs/IGBTs, buck inductor, output capacitor, and gate drivers? Control: What changes are required for ignition, warm-up current limiting, and constant-power regulation? Regards.

Hello,I have a question regarding a ballast and would appreciate some input from an ST engineer.How can I convert a 250W HID metal halide electronic ballast into a 400W HID metal halide electronic ballast? Also, could I use it to operate a 400W mercury UV lamp?

Hi! I’m slowly working my way through a design in which I plan to use the TCPP01-M12; my device is a USB-C sink, and I don’t intend to utilize any USB-PD negotiation. I have a conflict with my chosen MCU and the UCPD peripheral (the pins of this peripheral need to be allocated to another use), so I am interested in being able to read the CC lines of the USB connection to understand the power capabilities of the upstream source, without dealing with any actual CC communication.  The datasheet for the TCPP01-M12 shows this exact use, on Page. 18, Figure 20. As I understand it, I can use my ADCs to read the voltages on the CC pins to calculate the current delivery capability of the source. What confuses me, however, is that apparently the source will also try to start communicating over the CC lines on connection. As I understand it, this communication happens at a logic level of between 0-1V or so, regardless of the actual current carrying capabilities. The obvious problem is that if I s

Good day Sir & Madam, Could you please confirm if MPN STW11NK100Z is free of Dechlorane Plus?We currently have stock with date code 2410 (Year 2024, Week 10). Can you please verify if this specific batch contains Dechlorane Plus?

Hello ST team and community,ST Online Support recommended asking here after reviewing the product documentation. I am developing a battery-management hardware-in-the-loop (HIL) prototype and would appreciate authoritative protocol details and guidance on the remaining chip behaviors.Project contextAn Arty Z7-20 FPGA models ten independent 16S battery modules and ten logical L9965A CMUs, split across two VIF endpoints with five CMUs each. An STM32H753 is the external controller, communicating through real L9965T transceivers and a planned external isolated receive/drive front end. The FPGA is not connected directly to the analog ISO pins and does not replace the L9965T. Physical interoperability testing is still pending while hardware is being assembled.Implemented and tested in simulation: NORMAL-mode 40-bit single reads/writes, global/selective broadcasts, enumeration, standard cell-voltage bursts and CRC6 checked against ST's firmware calculator. The CMUs also implement coherent conv

I received VND5160JTR-65-E instead of VND5160JTR-E. Which are the differences between them? What do the additional characters ‘-65’ mean?