B-G431B-ESC1 Layout Question (Via Current)

[FKL]

Hello,

I have had a look over the B-G431B-ESC1 Layout Files and found that the High Side FETs are connected to V+ with a single Via.

The brown layer is V+, the large red pad is where the FET Drain is connected.

I can only see the single via i marked. The production files state the same.

This via can only carry about 1A of current, so this is definitely a design flaw.

Can you please check if there is a error in the design files I downloaded or if I am right.

@Laurent Ca...​ 

[Peter BENSCH]

The via you are pointing to is the connection of R68 to V+, who senses the bus voltages to VBUS.

But I also need to check where the other vias are.

Regards

/Peter

[Mariano Abad]

It looks like that via is the only connection from V+ to the FET Pads.

[FKL]

Thank you Peter.

Is there any news about this yet? Did you find internal data about the board, maybe only the public download files are incorrect/not up to date.

[Laurent Ca...]

Dear @FKL​ 

Could you give me the link of the layout documentation you referred in order to check consistency with internal ones?

Best regards

==

Laurent Ca...

[FKL]

Hi Laurent,

I downloaded the Altium Project files as well as the Gerber production files from this link:

https://www.st.com/en/evaluation-tools/b-g431b-esc1.html#cad-resources

There has been a new revision since I opened this thread but I checked and the 'error' is still in there 😉

Regards, Frieder

[Giuseppe Scuderi · Accepted solution]

Dear @FKL​ ,

thanks for your feedback. We are going to fix it and we will produce a new batch of the board soon.

Best regards,

Giuseppe Scuderi

[FKL]

Thank you for your reply! Glad I could help.

[dsamm]

@Giuseppe Scuderi_O​  could you please clarify if this an issue limits the max motor current ( for the board revision sold until end of Jan 2021).

br

daniele

[Giuseppe Scuderi]

Hi,

you can use it at full load without issues.

BR

G.