STM32F407IGT: I2C3 is working as expected but I2C1 and I2C2 have problems

[SMali.3]

I am looking for an expert to help me with I2C bus on STM32F407IGT. I2C3 is working as expected and I would like to make working also I2C1 and I2C2 which I have problems with.

I am using the same initialization regarding registers and I can see the right values on the right places (addresses) but I don't get any interrupt on I2C1 and I2C2. I set the start bit and a value in DR register but I can not see any clock or signal on pins. Any idea what to check?

[TDK]

Check that the GPIO clocks are enabled and the pins are set to the correct AF mode. Check the I2Cx registers and compare the values for the working I2C3 and the not-working I2Cx. Check that the global interrupts for I2Cx are enabled.

[SMali.3]

Hi TDK

I have checked all registers which has something to do with I2C devices and I did not see any inconsistencies for I2C1, I2C2 compared to I2C3 which is working fine. Here is the printout of checked registers:

I2C1:

   CR1 -> a=0x40005400: v=0x701

   CR2 -> a=0x40005404: v=0x72a

   OAR1 -> a=0x40005408: v=0x40a0

   OAR2 -> a=0x4000540c: v=0x0

   DR -> a=0x40005410: v=0x53

   SR1 -> a=0x40005414: v=0x0

   SR2 -> a=0x40005418: v=0x2

   CCR -> a=0x4000541c: v=0xd2

   TRISE -> a=0x40005420: v=0x2b

   FLTR -> a=0x40005424: v=0x0

   Using PB6->SCL, PB7->SDA:

       MODER -> a=0x40020400: v=0x8284

       OTYPER -> a=0x40020404: v=0x80

       OSPEEDR -> a=0x40020408: v=0x80cc

       PUPDR -> a=0x4002040c: v=0x104

       IDR -> a=0x40020410: v=0x1cd8

       ODR -> a=0x40020414: v=0x0

       BSRR -> a=0x40020418: v=0x0

       LCKR -> a=0x4002041c: v=0x0

       AFRL -> a=0x40020420: v=0x44000000

       AFRH -> a=0x40020424: v=0x0

I2C2:

   CR1 -> a=0x40005800: v=0x501

   CR2 -> a=0x40005804: v=0x72a

   OAR1 -> a=0x40005808: v=0x40a0

   OAR2 -> a=0x4000580c: v=0x0

   DR -> a=0x40005810: v=0x35

   SR1 -> a=0x40005814: v=0x0

   SR2 -> a=0x40005818: v=0x2

   CCR -> a=0x4000581c: v=0xd2

   TRISE -> a=0x40005820: v=0x2b

   FLTR -> a=0x40005824: v=0x0

   Using PF1->SCL, PF0->SDA:

       MODER -> a=0x40021400: v=0x140600a

       OTYPER -> a=0x40021404: v=0x43

       OSPEEDR -> a=0x40021408: v=0x3c0e00a

       PUPDR -> a=0x4002140c: v=0x1404000

       IDR -> a=0x40021410: v=0x8983

       ODR -> a=0x40021414: v=0x8c0

       BSRR -> a=0x40021418: v=0x0

       LCKR -> a=0x4002141c: v=0x0

       AFRL -> a=0x40021420: v=0x44

       AFRH -> a=0x40021424: v=0x0

I2C3:

   CR1 -> a=0x40005c00: v=0x1

   CR2 -> a=0x40005c04: v=0x72a

   OAR1 -> a=0x40005c08: v=0x40a0

   OAR2 -> a=0x40005c0c: v=0x0

   DR -> a=0x40005c10: v=0x97

   SR1 -> a=0x40005c14: v=0x0

   SR2 -> a=0x40005c18: v=0x0

   CCR -> a=0x40005c1c: v=0xd2

   TRISE -> a=0x40005c20: v=0x2b

   FLTR -> a=0x40005c24: v=0x0

   Using PH7->SCL, PH8->SDA:

       MODER -> a=0x40021c00: v=0x29000

       OTYPER -> a=0x40021c04: v=0x180

       OSPEEDR -> a=0x40021c08: v=0x2b000

       PUPDR -> a=0x40021c0c: v=0x1000

       IDR -> a=0x40021c10: v=0x180

       ODR -> a=0x40021c14: v=0x0

       BSRR -> a=0x40021c18: v=0x0

       LCKR -> a=0x40021c1c: v=0x0

       AFRL -> a=0x40021c20: v=0x40000000

       AFRH -> a=0x40021c24: v=0x4

RCC Registers:

   CR -> a=0x40023800: v=0x3037283

   PLLCFGR -> a=0x40023804: v=0x7405408

   CFGR -> a=0x40023808: v=0x940a

   CIR -> a=0x4002380c: v=0x0

   AHB1RSTR -> a=0x40023810: v=0x0

   AHB2RSTR -> a=0x40023814: v=0x0

   AHB3RSTR -> a=0x40023818: v=0x0

   APB1RSTR -> a=0x40023820: v=0x0

   APB2RSTR -> a=0x40023824: v=0x0

   AHB1ENR -> a=0x40023830: v=0x1011ff

   AHB2ENR -> a=0x40023834: v=0x0

   AHB3ENR -> a=0x40023838: v=0x0

   APB1ENR -> a=0x40023840: v=0x10ea4030

   APB2ENR -> a=0x40023844: v=0x24030

   AHB1LPENR -> a=0x40023850: v=0x7e6791ff

   AHB2LPENR -> a=0x40023854: v=0xf1

   AHB3LPENR -> a=0x40023858: v=0x1

   APB1LPENR -> a=0x40023860: v=0x36fec9ff

   APB2LPENR -> a=0x40023864: v=0x75f33

   BDCR -> a=0x40023870: v=0x0

   CSR -> a=0x40023874: v=0x1e000000

   SSCGR -> a=0x40023880: v=0x0

   PLLI2SCFGR -> a=0x40023884: v=0x20003000

Where are global interrupt for I2C located? Maybe someone else can again check the registers, probably I did not seen something.

Best regards

Simon

[TDK]

> I have checked all registers which has something to do with I2C devices and I did not see any inconsistencies for I2C1, I2C2 compared to I2C3 which is working fine.

I2C1:

   CR1 -> a=0x40005400: v=0x701

I2C2:

   CR1 -> a=0x40005800: v=0x501

I2C3:

   CR1 -> a=0x40005c00: v=0x1

These don't seem consistent to me.

[SMali.3]

This is an indication that I2C1 and 2 doesn't work that is why the bits are set. The question here is what to do to make I2C1 and 2 work. For this two ports I am setting start bit writing to DR reg every 100ms and for I2C1 also setting the stop bit. Just to see some action on the ports which does not happens. Pullup 10K is present on both ports. Is this the wrong procedure to get something send on ports?

[Amel NASRI]

Hi @SMali.3​ ,

As you see in the I2C_SR2 register, the Busy bit is set for I2C1 & I2C2.

Make sure that the I2C pins are configured before enabling the I2C clock.

-Amel

[SMali.3 · Accepted solution]

Hi Amel

Thank you very much for your suggestion. Actually this was reason for I2C1 bus not working. After enabling the clock as a last step in initialization routine now I2C1 works as expected.

Regards

Simon