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Performances reduced when migrating from L476 to L562 ?

advFR
Associate

Hello,

I have a small application running on a nucleo-L476RG board. This application is testing a G729 codec (to encode audio samples). It allows me to measure the time required to encode and to decode a 10ms audio record. For testing purpose, the "audio record" is a sinusoidal signal stored in a table in memory.

I have tried to use this code on a board with a STM32L562. I was pretty sure that the performances will be better and that the encoding/decoding time will be reduced, or at least the same.

Surprise! With the L562, it is about 2x times slower than with the L476... Frequency is the same for the two boards (80MHz), optimisation level is set to -Ofast, every option in project configuration are the same. The two projects are generated the same way using CubeIDE 1.5.0.

Is there something I have possibly missed ?

Thanks for your help.

Note : I have tried the L562 with 110 or 80MHz clock with no significant differences. I suppose that this is due to architecture rather than frequency ?

2 REPLIES 2
Ozone
Lead

Different Flash settings (wait states) ?

At least the other families had a transparent, 128 bit wide cache system called ART for instruction fetch.

Perhaps "random" code alignment differences between both MCUs ?

I haven't tested any L4xx or L5xx yet.

Amel NASRI
ST Employee

Hi @advFR​ ,

The STM32L5 devices reuse STM32L4 & STM32L4+ Series technologies, and they add security features thanks to the Cortex-M33.

In terms of CPU performance, it depends on the Vcore range, the number of wait states and the expected power performance.

The following table that you may find in AN5138 (Migrating from STM32L4 and STM32L4+ to STM32L5 Series microcontrollers) summarizes the differences:

0693W000006GtktQAC.pngIn order to more enhance the performance for your STM32L5 device, I recommend you to refer to the application note AN5212 (Using STM32L5 Series cache to optimize performance and power efficiency).

-Amel

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