STM32G070RBT6 effective speed when running on 64MHz

[Slina]

I've read in RM that, when running on 64 MHz it has 2 wait states, meaning that 1 cycle instructions execution takes actually 3 cycles. If I understand this correctly, that means that the effective speed is actually 21.3 MHz? What use is there using 64 MHz then? Or there is parallel pipelines for instruction execution? What is then effective speed, if there are two pipelines?

[STOne-32 · Accepted solution]

Dear @Siniša Marović​ 

That is a nice question ! I Invite you to jump to our On-line Training here - your can go to Slide 13 directly where we explain how our Flash and Flash accelerators are working to get the best performance with the core running at 64MHz :

https://st-onlinetraining.s3.amazonaws.com/STM32G0-Memory-Flash-%28FLASH%29/index.html

and also the Cortex-M0+ Introduction and Pipeline with the instruction set

https://st-onlinetraining.s3.amazonaws.com/STM32G0-System-ARM_Cortex_G0-%28Core%29/index.html

Cheers,

STOne-32.

[Slina]

Yes, that's what I needed. So, if I understand correctly, for linear code block with prefetch and instruction cache on, simple load/store instructions should be executed at speed of 1 instruction per cycle. Even to ports?