Can anyone point me to "soft error" stats on the STM32L452 SRAM and Flash arrays? Lacking that, can anyone tell me what design rule/geometry the SRAM and Flash arrays use (in nm), from which I can estimate the stats?

[Tesla DeLorean]

The L4 uses 90nm, defused out of ST Crolles CRL300 (France) [VQ] or TSMC Fab14 (Taiwan) [9R]

I'm sure the sales or FAE assigned to your account can give you specific stats.