cancel
Showing results for 
Search instead for 
Did you mean: 

DMA issues with dual-core STM32H745

TypeKazt
Associate III

I'm currently using the dual-core STM32H745, and am trying to utilize DMA's on both cores to R/W to/from shared memory. DMA's are only successful on the M4 cores, and always yield a DMA Transfer Error. I haven't done anything to modify the initialization of the DMA peripherals between cores (Cube by default initializes all the DMA's selected on both cores).

1 ACCEPTED SOLUTION

Accepted Solutions
Bouraoui Chemli
ST Employee

Hi @TypeKazt​ 

DMA can't access to DTCM SRAM. It is the product architecture, only MDMA have access to DTCM RAM.

By default in CubeMx the RW data are located in DTCM RAM. if you declare a buffer, and give its address as a parameter to DMA, the transfer will fails.

D2SRAM, D3SRAM or AXISRAM can be used for DMA transfers.

For more details about memory and bus architecture you can refer to section 2 of RM0399 Rev 3

View solution in original post

3 REPLIES 3
Bouraoui Chemli
ST Employee

Hi @TypeKazt​ 

DMA can't access to DTCM SRAM. It is the product architecture, only MDMA have access to DTCM RAM.

By default in CubeMx the RW data are located in DTCM RAM. if you declare a buffer, and give its address as a parameter to DMA, the transfer will fails.

D2SRAM, D3SRAM or AXISRAM can be used for DMA transfers.

For more details about memory and bus architecture you can refer to section 2 of RM0399 Rev 3

TypeKazt
Associate III

I did allocate space in D2SRAM in the linker and assign a buffer the memory attribute, but it was still failing. Could there be some conflict caused between the two cores both initializing the same DMA? Alternatively, I haven't tried using the MDMA peripheral for MEMTOMEM transfers, so I suppose I can try that as well.

TypeKazt
Associate III

Thanks @Bouraoui Chemli​ , the MDMA works fine on the M7.

A related question would be whether the performance of the MDMA and DMA for MEMTOMEM writes is identical. The assumption being that if two DMA's access the same buffer it will prevent a race condition/memory corruption from ever occurring since they have the same peripheral clock. It's difficult to infer this from the reference manual based on the different architecture of the peripherals.