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How does the USB peripheral behaves in the scenario where a single endpoint is configured for both bulk transmission and reception with double buffer mechanism?

GauravKumar
Associate

Hello,

I am using MCU STM32F303VC controller with USB 2.0 FS configuration as device and PC as the host.

CDC interface is configured to handle the Bulk transactions, and for this only 1 endpoint (Endpoint 1) has been used for handling both IN and OUT bulk transactions. This is done with double buffer mechanism in consideration.

There is no problem with the Control transfers on Endpoint 0. For the Bulk transfers on Endpoint 1, there is no problem when the rate of IN/OUT transactions is low

But for the bulk transactions, whenever the rate of IN/OUT transactions is relatively higher, sometimes the USB peripheral is not triggering the interrupt for OUT transaction.

At this point, STAT_TX and STAT_RX values for Endpoint 1 are NAKed.

Further looking into the reference manual (RM0316_ReferenceManual), the following description is found:

In case it is required to have double-buffered bulk endpoints enabled both for reception and transmission, two USB_EPnR registers must be used.

In the manual, it is not clearly mentioned about the USB peripheral behavior in case a single endpoint is configured for both IN and OUT transactions.

I need information on below points:

1.   How does the USB peripheral behaves in the scenario where a single endpoint is configured for both bulk transmission and reception? What would be the consequences under this configuration?

2.   Is this a recommended way to handle bulk transactions by configuring a single endpoint to handle both IN and OUT transactions?

3. Is there an example available for the implementation of bulk endpoints considering double buffer mechanism, demonstrating the handling of DTOG and SW_BUF bits for the configured bulk endpoint?

Thanks & Regards,

Gaurav

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