on page 997 of RM0433 Rev 7 it first says 2 bytes are transferred each DMA request, and then that 4 bytes are transferred each DMA request:
DAMDF=0b11: This mode is similar to the DAMDF=0b10. The only differences are that
on each DMA request (two data items are available), two bytes representing two ADC
converted data items are transferred as a half-word.
This mode is used in interleaved and regular simultaneous mode when the result is 8-
bit. A new DMA request is issued when 4 new 8-bit values are available.
The given example also says 4 bytes.
When testing the first statement seems to be true: the DMA request is issued after 2 new 8-bit values are available in last half-word of the CDR register.
On page 1046 it confirms this:
In MDMA=0b11 mode, bits 15:8 contains SLV_ADC_DR[7:0], bits 7:0 contains
MST_ADC_DR[7:0].
Only MDMA must be changed to DAMDF in this sentence.
Furthermore the following statements contradict each other:
page 997:
When DAMDF mode is selected (0b10 or 0b11), bit DMNGT[1:0]=0b10 in the master ADC’s
ADCx_CCR register must also be configured to select between DMA one shot mode and
circular mode
page 1020: about DMNGT register
In dual-ADC modes, this bit is not relevant and replaced by control bit DAMDF of the
ADCx_CCR register.
It seems the note on page 1020 is incorrect, and should be deleted.
Please check and update RM0433. Thanks!
