QUADSPI timings to read, write, erase flash IC

[AShel.1]

Hello,

I've a MT25QL128 IC interfaced with STM32F767 controller on QUADSPI. there is external crystal of 8MHz. I want to check timings req for read, write and erase the flash IC, so that I can write some data into flash. I've referred application note but could not calculate the exact timings. please help me with some references.

https://www.st.com/resource/en/application_note/dm00227538-quadspi-interface-on-stm32-microcontrollers-and-microprocessors-stmicroelectronics.pdf

Thanks in advance

[Tesla DeLorean]

Presumably the core's clocking based on the PLL settings, and not off the external clock directly.

Timings going to depend on the AHB, and described in the flash IC's data sheet.

Erase is not bound by bus timing, both it and Write will need to spin on the status register of the flash IC to wait for it to come READY or be NOT BUSY

Long term timing can be measured with the SysTick interrupt/counter

Examples can be found in the Drivers/BSP sections for various F7 DISCO and EVAL boards within the CubeF7 directory trees (repository)

[AShel.1]

Thanks Clive,

MT25QL128 supports clock freq of 90MHz, so clock cycle time will be ? I'm not able to ficure out how its coming 57.22Mb in following explaination from application note

from application note:

For instance, if the user hardware allows the QUADSPI to operate at 60 MHz in DDR Quad I/O mode, then for a sequential access case, an image can be read at 60000000/1024/1024= 57.22 Mbyte/s. In this case for a 4 Kbytes image, the total transfer time is of 4107 cycles: eight cycles for command + three cycles for the address (24 bits in DDR mode) + 4096 cycles for the 4 Kbytes image

[Tesla DeLorean]

MB (Byte) not Mb (bit)

1024/1024 gets you to a megabyte

60 would be halved at 4-bit wide, but DDR (Double Data Rate) gets 4-bit on each edge of the clock.

There is some cycle overhead sending commands/addresses, but over longer bursts the QSPI implementation is pretty efficient.

At 90 MHz SDR, 90,000,000 / 2 / 1024 / 1024 -> 42.9 MB/s

90 MHz cycle is 11.11 ns

Problem likely will be you're clocking the F7 at 216 MHz, 216/4 = 54 MHz, 216/3 = 72 MHz, so you'll end up derating the part, or you can run the F7 slower to gain the edge on the QSPI XIP performance. Anyway, at these speed you likely want series resistors on short lines to reduce ringing, and back off on the slew rate (speed) settings on the pin driver.

STM32Cube_FW_F7_V1.16.0\Drivers\BSP\STM32F769I-Discovery\stm32f769i_discovery_qspi.c

 /* QSPI initialization */

 /* QSPI freq = SYSCLK /(1 + ClockPrescaler) = 216 MHz/(1+1) = 108 Mhz */

 QSPIHandle.Init.ClockPrescaler   = 1;  /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */

 QSPIHandle.Init.FifoThreshold   = 16;

 QSPIHandle.Init.SampleShifting   = QSPI_SAMPLE_SHIFTING_HALFCYCLE;

 QSPIHandle.Init.FlashSize     = POSITION_VAL(MX25L512_FLASH_SIZE) - 1;

 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_4_CYCLE; /* Min 30ns for nonRead */

 QSPIHandle.Init.ClockMode     = QSPI_CLOCK_MODE_0;

 QSPIHandle.Init.FlashID      = QSPI_FLASH_ID_1;

 QSPIHandle.Init.DualFlash     = QSPI_DUALFLASH_DISABLE;

 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)

 {

  return QSPI_ERROR;

 }

STM32Cube_FW_F7_V1.16.0\Drivers\BSP\STM32F7508-Discovery\stm32f7508_discovery_qspi.c

 /* QSPI initialization */

 QSPIHandle.Init.ClockPrescaler   = 1; /* QSPI freq = 216 MHz/(1+1) = 108 Mhz */

 QSPIHandle.Init.FifoThreshold   = 4;

 QSPIHandle.Init.SampleShifting   = QSPI_SAMPLE_SHIFTING_HALFCYCLE;

 QSPIHandle.Init.FlashSize     = POSITION_VAL(N25Q128A_FLASH_SIZE) - 1;

 QSPIHandle.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_6_CYCLE; /* Min 50ns for nonRead */

 QSPIHandle.Init.ClockMode     = QSPI_CLOCK_MODE_0;

 QSPIHandle.Init.FlashID      = QSPI_FLASH_ID_1;

 QSPIHandle.Init.DualFlash     = QSPI_DUALFLASH_DISABLE;

 if (HAL_QSPI_Init(&QSPIHandle) != HAL_OK)

 {

  return QSPI_ERROR;

 }

[AShel.1]

Thanks for detailed info,

is it possible to log some data before power goes off, may be some low voltage detection mechanism I'll have to add and before it shuts down some logs to be written to flash.

in eval board this feature may not be included. so need some help to design this.

Thanks in advance

[AShel.1]

Thanks for detailed info,

is it possible to log some data before power goes off, may be some low voltage detection mechanism I'll have to add and before it shuts down some logs to be written to flash.

in eval board this feature may not be included. so need some help to design this.

Thanks in advance

[Tesla DeLorean]

Depends if you think you can out run the collapsing supply with something slow and power consuming.

People would normally flush such data to NVRAM, with a battery/supercap behind it, and shutdown.