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STM32H745/755 cores frequency after reset is not the same?

binarybee
Associate III

Hi guys, I read reference manual for STM32H745/755, where is mentioned that the both CPUs are after reset running on the same clock frequency, because they shared the same clock source and the prescalers are after reset in default state (no division of clock signal). I did stupid test in main loop with blinking LEDs driven separately (each on one core), but they are blinking with different period. I didnt set up anything else, interrupts are not allowed but I cant find the reason of different LEDs blinking period.

Thanks a lot for advices!

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1 ACCEPTED SOLUTION

Accepted Solutions
berendi
Principal

The more advanced pipeline and branch predictor in the M7 core can make a big difference.

Moreover the M7 core has a direct 64 bit path to the flash memory, while the M4 core goes through a 32-to-64 bit gateway with caching disabled. So the M7 can benefit from its 64 bit prefetch unit (which is I think always active), while the M4 must make separate accesses for each 32 bit word in the flash.

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3 REPLIES 3
berendi
Principal

They have different cores, so the execution time of some instructions are different.

They are not connected in the same way to the system bus, and have different caches, so the time they need to read their program from the flash is not the same. See Figure 1. System architecture for STM32H745/55/47/57xx devices in the reference manual.

Hi, thanks for reply, the difference in period is really big, maybe two times faster, I guess this is not caused by different execution time and Im not using caches for M7.

berendi
Principal

The more advanced pipeline and branch predictor in the M7 core can make a big difference.

Moreover the M7 core has a direct 64 bit path to the flash memory, while the M4 core goes through a 32-to-64 bit gateway with caching disabled. So the M7 can benefit from its 64 bit prefetch unit (which is I think always active), while the M4 must make separate accesses for each 32 bit word in the flash.