STM32G030 DMA to GPIO BSRR bus error

[Chan.Calvin]

Hi

STM32G0 series is a newer chip family with more advanced DMA/MUX to provide more flexibility.

my code, which uses tim16 update to request DMA to transfer from memory to GPIO BSRR. The code works on STM32F030 but fail in G030. The request from TIM16 gets through DMA, and it is the DMA that flags the transfer error.

Can anyone confirm that this is the case? From the reference manual, it seems that DMA and GPIO are in different bus that makes my intention impossible.

Rgds

Calvin

[TDK]

You should be able to do DMA transfers from memory to GPIOB->BSRR without issue. What error is it giving you?

[waclawek.jan]

Read out and post content of DMAMUX and DMA registers.

JW

[Chan.Calvin]

I can only see both the GIF and TEIF flags in the DMA ISR register set, implying the transfer error. With the DMA CNDTR remains unchanged. Meaning that the transfer error happens at the 1st data transfer (from memory to GP!OA BSRR).

Note: If I change the destination as memory and do memory to memory transfer, the code works.

But looking from the reference manual - RM0454 section 2, the diagram shows GPIO port bus and DMA bus may not be "connected".

I am off work until next Monday, so I can only get the register details by then.

Calvin

[TDK]

Ahh, I think you are correct. My mistake.

[waclawek.jan]

Indeed - the 'G0 (as well as 'L0) is Cortex-M0+ which has a special port on the processor for GPIO, so you can't DMA onto GPIOs.

My mistake too... 🙂

JW

[MSipo]

This happened to me today. Glad to find an answer. =) But unhappy I can't trigger DMA to GPIO using a timer. :loudly_crying_face:

Read more here: https://www.st.com/resource/en/product_training/STM32G0-System-General-purpose-IO-interface-GPIO.pdf

"I/O ports are directly connected to the single-cycle IO port bus. This allows fast I/O pin operations, e.g. toggling of the pin every two clock cycles. No conflict with the DMA can occur because this Cortex®-M0+ port is private to the CPU."