No CRC error in reception even is MISO not connected on STM32H7 SPI ??

[Gpeti]

Hello,

This question is the follow-up of this one:

https://community.st.com/s/global-search/Setting%20of%20GPIO%20PUPDR%20and%20OTYPER%20for%20SPI%20pins

I thought I had fixed it thanks to the GPIO setting but it was just bad luck.

My setup is:

• two Nucleo STM32H743
• the master is using on SPI1
• the slave is using SPI2 (with SPI1 I have no issue)
• clock setup is: for master VOS1, Sysclk 400MHz, HCLK 200, PCLK 100, spi_ker_clk 200 and SPI baudrate prescaler at 8. For master every clock divided by 2 (parameter M to setup ref1_ck of PLL1 was changed)
• GPIO: high freq / push-pull / no pull down (tried with pull down, no difference)
• slave receives correctly all the time
• master never receives answer from the slave
• SPI setup at master side to receive the answer from slave: simplex receive only, CRC enabled, datawidth 8 bits, 5 bytes to receive

I completely unplugged the MISO wire. On master side I of course still gets the EOT event (as expected) but I expect to get a CRC error since I should receive crappy data , perhaps random or all 0 bytes. But I have no error status in SPI1_SR.

How is it possible that a receive only SPI with CRC enabled detects no CRC error in this case ?

[Tesla DeLorean]

Does it receive all zeros?​

[Dvorak.Peter]

Try it with 10k pullup on MISO

[Gpeti]

Sorry, I tried to delete the post but it seems it doesn't work ? I thought the CRC of a set of 0 bytes was not zero, because I took the wrong CRC configuration. But actually I receive only zeros so the CRC is "correct".

[Tesla DeLorean]

Typically depends what the CRC is initialized with. Specific patterns will also clear the register.

If you feed the computed CRC through the check the "remainder" drops out to zero. That's how the SPI checks, it is a CRC==0 of Data+CRC rather than CRC==expected value.