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STM32H7 - SAI sampling frequency is 45.5kHz instead of 44.4kHz

Mdi c
Associate III

Dear all, I am using SAI in STM32H7 to control an external audio codec. Everything works fine except the fact that when I look at the actual sampling frequency (SAI FS signal ) I measure 45.5kHz rather than 44.1kHz as specified in the init. The clock of the SAI is 128M. Do you know what i should look at to get the closest frequency possible ?

1 ACCEPTED SOLUTION

Accepted Solutions

> Do you know what i should look at to get the closest frequency possible ?

You did not tell us what protocol/dividers are you using, but it appears that you have the fundamental divider of 256 (i.e. you need to generate MCLK which is 256xLRCLK (sample clock)) which constrains you to fkernel/11/256=45.45kHz.

You need to work backwards, starting from the desired sampling frequency (i.e. 44.1kHz), multiply it with the fundamental divider i.e. 256 = 11289600Hz, and then generate kernel clock which is integer multiple of this frequency.

Use either a different primary clock source, one which is integer multiple of 44.1kHz and then work towards the needed SAI kernel clock; or if you don't mind the increased jitter, use the fractional PLL to generate the SAI kernel clock from whatever primary clock source you have.

Spreadsheets are your friend.

JW

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2 REPLIES 2
DFuchs
Associate III

Hi,

i would start with SAI block diagram. For STM32H743 i see some clocks (sai_a, sai_b, sai_pclk, ker_ck).

In the Kernel clock distribution overview i see different possible clock sources for SAI1..4.

So check which kernel source you are using and if it is working correct.

Kind regards

Daniel

> Do you know what i should look at to get the closest frequency possible ?

You did not tell us what protocol/dividers are you using, but it appears that you have the fundamental divider of 256 (i.e. you need to generate MCLK which is 256xLRCLK (sample clock)) which constrains you to fkernel/11/256=45.45kHz.

You need to work backwards, starting from the desired sampling frequency (i.e. 44.1kHz), multiply it with the fundamental divider i.e. 256 = 11289600Hz, and then generate kernel clock which is integer multiple of this frequency.

Use either a different primary clock source, one which is integer multiple of 44.1kHz and then work towards the needed SAI kernel clock; or if you don't mind the increased jitter, use the fractional PLL to generate the SAI kernel clock from whatever primary clock source you have.

Spreadsheets are your friend.

JW