Static latch-up test as per JESD78A, which over-voltage profile is applied during the test?

[AAvan.1]

The STM32F407xx datasheet (DocID022152 Rev 😎 specifies on page 113 that a supply overvoltage is applied to each power supply pin, in conformance to the EIA/JESD 78A. What is the applied voltage profile? The standard specifies 1.5 x Vmax for a T up to 1 sec. therefore I am asking what are Vmax and T considered. Thank you.

[AAvan.1]

I see that most probably the question was not issued in the right place. Can someone please provide a technical contact where to address the question? Thank you.