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H3LIS100DL sleep-to-wake - how to enable?

cphelan
Associate II

Greetings. I am familiar with the general sleep-to-wake functionality, I've used it successfully in the IIS2DH. However I am having issues with the H3LIS100DL. I believe I've enabled sleep-to-wake using control register 5, I've configured the interrupt using int1_cfg, int1_duration and int1_ths, and I can view interrupt events occurring using the Unico interface. However I cannot "see" the change in output data rate from an interrupt state to a non-interrupt state in the Unico plot screen. Admittedly not scientific, however the transition was very obvious when using the IIS2DH.

Based on my understanding, when the interrupt is active, I should have a ODR per the setting in ctrl_reg1 (400Hz in my case) and the power mode should jump from low power to normal mode. While not explicitly stated, my assumption is that, in the low power/interrupt-not-active state, the ODR should be 10Hz max (since this is the max possible in low power mode). If this is true, then certainly I should be able to see (via Unico) the ODR change from 10Hz to 400Hz.

I did also notice that control register 5 auto updated after an interrupt event. To enable sleep-to-wake mode, control register 5 is set to 0x03. After an interrupt, it auto updates to 0x01. Not sure why, not sure of the implications, just merely an observation (perhaps it is indicative of something I am doing wrong).

Anyway, any assistance to getting this set up properly would be very helpful. Like I said, I have the host board and the Unico interface, so I can tweak/test quickly.

Thanks,

Chris

2 REPLIES 2
Eleon BORLINI
ST Employee

Hi @cphelan​ , the settings seems ok, but the minimum detectable signal of the H3LIS100DL is much higher (up to 780mg) that the same parameter of IIS2DH (1mg or 4 mg depending on the working mode). Maybe the sleep-to-wake function is not activated due to the fact that this signal is below the sensitivity.

The sleep-to-wake function is described in datasheet as follows:

Setting TurnOn[1:0] bits to 11, the “sleep-to-wake�? function is enabled. When an interrupt event occurs, the device is turned to normal mode, increasing the ODR to the value defined in CTRL_REG1. Although the device is in normal mode, CTRL_REG1 content is not automatically changed to “normal mode�? configuration.

Regards

cphelan
Associate II

Thanks, I was setting the power mode to normal, assuming it would drop to a low power state when an interrupt was not active (like the IIS2DH). Apparently I needed to do the opposite. Thanks for your help!