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Is there any relation between maximum SDIO clock and core system clock?

Hbehe.1
Associate

Hello,

I am working on SDIO in STM32F76 micro controller.

SDIO clock frequency is 24MHZ derived form 48MHz PLL (48MHz/2 MHz), Bus Width is 4 Bit.

SD card is working fine with system core clock 48Mhz but it is not working with system clock 24Mhz.

Same issue is observed in STM32F746G discovery board with sample code.

PCLC2 is 24MHz which also satisfied following equation. 

Frequenc(PCLK2) > ((3xWidth) / 32) × Frequency(SDMMC_CK) 

Clock configuration summary as below.

  --------------------------------------------------------------------------

 *    System Clock source          | HSE

 *-----------------------------------------------------------------------------

 *    SYSCLK(Hz)               | 192000000

 *-----------------------------------------------------------------------------

 *    HCLK(Hz)                | 24000000

 *-----------------------------------------------------------------------------

 *    AHB Prescaler             | 8

 *----------------------------------------------------------------------------

 *    APB1 Prescaler             | 1

 *-----------------------------------------------------------------------------

 *    APB2 Prescaler             | 1

 *-----------------------------------------------------------------------------

 *    HSE Frequency(Hz)           | 25000000

 *-----------------------------------------------------------------------------

 *    PLL_M                 | 25

 *-----------------------------------------------------------------------------

 *    PLL_N                 | 384

 *-----------------------------------------------------------------------------

 *    PLL_P                 | 2

 *-----------------------------------------------------------------------------

 *    PLL_Q                 | 8

 *-----------------------------------------------------------------------------

 please guide me to resolve this issue.

  

Regards,

Hardik Behere

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