I am working on NUCLEO-F103RB (target STM32F103RB) with Keil uVision5. What I want to do is to trigger ADC1 injected group with TIM2 CC1 event every 10 microseconds, but it not work. Could anyone help me ？

[Silvano]

I have written ADC1_2_ IRQ Handler ISR and TIM2_IRQHandler. TIM2_IRQHandler is executed but ADC1_2_IRQHandler it is not executed.

I have also tried to trigger ADC1 injected group with JSWSTAR event and it works fine (ADC1_2_IRQHandler is executed).

The trouble exists booth whith simulator and with true hardware.

So I don't know why TIM2 CC1 event not work,  

Thanks, following is my code (only initialization and ISR)

  /*----------------------------------------------------------------------------
   * Initialization function
   *--------------------------------------------------------------------------*/  
 
void initialize(void)
{
  int index = 0;
  
  /* - SYSCLK clock = 72 MHz
     - HCLK clock (Core clock) = 72 MHz  (AHB prescaler = /1)
     - PCKL1 clock  = 36 MHz (APB1 prescaler = /2 usato da TIM2 e PORT)
     - PCKL2 clock  = 72 MHz (APB2 prescaler = /1 usato da ADC2) 
     - TIM2CLK      = 72 MHz
  */
 
 
  /*----------------------------------------------------------------------------
   * TIM2 configuration
   *--------------------------------------------------------------------------*/  
  
  RCC->APB1ENR  |= RCC_APB1ENR_TIM2EN;
  
  /* Overflow frequency =  TIM2CLK / ((TIM2_PSC + 1) * (TIM2_ARR + 1)).
     At reset TIM2_PSC = 0.
     If TIM2_ARR = 719 than
     overflow frequency =  TIM2CLK / ((TIM2_PSC + 1) * (TIM2_ARR + 1)) =
     72 MHz / ((0 + 1) * (719 + 1)) = 100 kHz. */
  TIM2->ARR   =  719;  
  TIM2->CCR1  =  TIM2->ARR;
  TIM2->CCMR1 |= (0 * TIM_CCMR1_OC1M_2) | (0 * TIM_CCMR1_OC1M_1) 
              |  (1 * TIM_CCMR1_OC1M_0); 
  TIM2->CR1   |= TIM_CR1_CEN;
  TIM2->DIER  |= TIM_DIER_CC1IE;
  NVIC_EnableIRQ(TIM2_IRQn);
 
 
  /*----------------------------------------------------------------------------
   * PB1 as ADC_IN9 configuration
   *--------------------------------------------------------------------------*/
  
  RCC->APB2ENR  |= RCC_APB2ENR_IOPBEN;
  GPIOB->CRL    |= (0 * GPIO_CRL_MODE1_1) | (0 * GPIO_CRL_MODE1_0);
  GPIOB->CRL    &= ~GPIO_CRL_CNF1;
  GPIOB->CRL    |= (0 * GPIO_CRL_CNF1_1)  | (0 * GPIO_CRL_CNF1_0);
 
 
  /*----------------------------------------------------------------------------
   * PC4 as ADC_IN14 configuration
   *--------------------------------------------------------------------------*/
 
  RCC->APB2ENR  |= RCC_APB2ENR_IOPCEN;
  GPIOC->CRL    |= (0 * GPIO_CRL_MODE4_1) | (0 * GPIO_CRL_MODE4_0);
  GPIOC->CRL    &= ~GPIO_CRL_CNF4;
  GPIOC->CRL    |= (0 * GPIO_CRL_CNF4_1)  | (0 * GPIO_CRL_CNF4_0);
 
 
  /*----------------------------------------------------------------------------
   * ADC clock configuration
   *--------------------------------------------------------------------------*/
  
  /* ADCPRE = 10b ==> ADCCLK = PCLK2 / 6 = 72MHz / 6  = 12 MHz */
  RCC->CFGR     |= (1 * RCC_CFGR_ADCPRE_1) | (0 * RCC_CFGR_ADCPRE_0);
 
 
  /*----------------------------------------------------------------------------
   * ADC1 configuration
   *--------------------------------------------------------------------------*/
 
  RCC->APB2ENR  |= RCC_APB2ENR_ADC1EN;
  ADC1->JSQR    |= (0 * ADC_JSQR_JL_1) | (1 * ADC_JSQR_JL_0);
  ADC1->JSQR    |= (0 * ADC_JSQR_JSQ3_4) | (1 * ADC_JSQR_JSQ3_3)
                |  (0 * ADC_JSQR_JSQ3_2) | (0 * ADC_JSQR_JSQ3_1)
                |  (1 * ADC_JSQR_JSQ3_0);
  ADC1->JSQR    |= (0 * ADC_JSQR_JSQ4_4) | (1 * ADC_JSQR_JSQ4_3)
                |  (1 * ADC_JSQR_JSQ4_2) | (1 * ADC_JSQR_JSQ4_1)
                |  (0 * ADC_JSQR_JSQ4_0);
  ADC1->JOFR1 = (1UL << 11); /* 2^11 = 2048 */
  ADC1->JOFR2 = (1UL << 11); /* 2^11 = 2048 */
  ADC1->SMPR2   |= (0 * ADC_SMPR2_SMP9_2) | (0* ADC_SMPR2_SMP9_1)
                |  (0 * ADC_SMPR2_SMP9_0);
  ADC1->SMPR1   |= (0 * ADC_SMPR1_SMP14_2) | (0* ADC_SMPR1_SMP14_1)
                |  (0 * ADC_SMPR1_SMP14_0);
  ADC1->CR2     |= ADC_CR2_ADON;   
  
  /* This for cycle generates a delay greater than Tstab. From datasheet
     Tstab max = 1 microsecond */
  for (index = 0; index < 72; index++)  
  {
    __NOP();
  }
 
  ADC1->CR1     |=  ADC_CR1_JEOCIE;   
  ADC1->CR1     |=  ADC_CR1_SCAN;
  ADC1->CR2     |= ADC_CR2_JEXTTRIG;
  ADC1->CR2     |= (0 * ADC_CR2_JEXTSEL_2) | (1 * ADC_CR2_JEXTSEL_1)
                |  (1 * ADC_CR2_JEXTSEL_0);
  NVIC_EnableIRQ(ADC1_2_IRQn);
  ADC1->CR2     |= ADC_CR2_CAL;   
  while(ADC1->CR2 & ADC_CR2_CAL)  
  {
  }    
}
 
/*------------------------------------------------------------------------------
  ISR ADC
 *----------------------------------------------------------------------------*/
 
volatile uint32_t counter_executions_ADC1_2_IRQHandler = 0; 
 
void ADC1_2_IRQHandler(void)
{
  ADC1->SR &= ~ADC_SR_JEOC;
  counter_executions_ADC1_2_IRQHandler++;
}
 
/*------------------------------------------------------------------------------
  ISR TIM2
 *----------------------------------------------------------------------------*/
 
volatile uint32_t counter_executions_TIM2_IRQHandler = 0; 
 
void TIM2_IRQHandler(void)
{
  TIM2->SR &= ~TIM_SR_CC1IF;
  counter_executions_TIM2_IRQHandler++;
}