cancel
Showing results for 
Search instead for 
Did you mean: 

STM32H743ZI spi communication is not working at Baud rate 80 Mbps or even greater than 40 Mbps

kgang
Associate II

Hi,

I have configured STM32H743ZI spi1 as master and spi2 as slave and code is generated using stm32cubemx spi is successfully working till 30 Mbps.but if configured at Baud rate of 80 Mbps or even greater than 40 Mbps slave is not able to receive data. But it should work till 150Mbs according to datasheet. What all changes i need to make sure to work at desired baud rate.

Any solutions will be highly appreciated .

regards,

Krishna

5 REPLIES 5
Ozone
Lead

> but if configured at Baud rate of 80 Mbps or even greater than 40 Mbps slave is not able to receive data. But it should work till 150Mbs according to datasheet.

Are you sure your physical bus design (PCB traces / wiring) has proper complex impedance and termination to support such a high clock frequency ?

According to Fourier it should be good for spectral components up to 1 GHz.

berendi
Principal
  • Set GPIO->OSPEEDR register bits for the pins involved to 11
  • Make sure spi123 kernel clock is actually 480 MHz. Check RCC_D2CCIP1R_SPI123SEL bits, and the PLL values selected by these bits.
  • If it's a nucleo board, check the board schematics and any jumpers/bridges that the SPI lines are not connected to any onboard peripheral.
  • Don't use HAL at those speeds

The OP wrote:

> ...code is generated using stm32cubemx spi is successfully working till 30 Mbps.

A seasoned engineer would take a scope, and check the CLK waveform. Which is an art in itself at this frequencies.

And probably see there is almost nothing left ...

S.Ma
Principal

True, oscilloscope is a must before checking protocols and packet with logic analyser.

I would guess that if the SPI bus is only within the same board, and if no glitch, 80 mbps might be the limit.

For board to board up to 1 meter (13 boards on same SPI bus), 12 mbps works.

For F4/L4 the max slave bit rate is 1/4 of SYSCLK and master is 1/2 of SYSCLK.

Piranha
Chief II