I plan to use STNRGPF01 to buil a PFC, eval board comes with 2 74HC132 package that are quit huge regarding the STNRG size.
I would prefer to use single gate and TRUE D flip flop with set reset...
knowing precise timings for Set and Reset will be a great help....
by the way ... why STN don't directly perform these PWM output? a mess to have external glue logic like these... ?
moreover at startup NAND gate output are undifened, fortunatly some capacitor are here to fix that on eval board
regards
