I have a question,when changed cpu from stmf407 to stm32f427 .sometimes, read a wrong data from extern sram access by FMC ,it's happend in most of the cases in interrupt ，someone have the same problem?

cxiao.6 · ‎2020-01-15

my English is poor，In the same program ,cpu 407 do not have this problem,only happened in 427，somtimes.It's like 2.3.4 Corruption of data read from the FMC. in <Errata sheet - STM32F42xx and STM32F43xx - STM32F427/437 and STM32F429/439 line limitations>,but it says ,This limitation is present only in revision “A�? devices. It is fixed in revision “Y�?, “1�?, “3�? and “5�? and “B�?. My revision is “3�?，there is someone have the same question?

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waclawek.jan · ‎2020-01-15

Can't this be a hardware problem, e.g. bad solder joint?

Is this still the same board, only with a different mcu?

And the system clock frequency did change or not?

JW

Ozone · ‎2020-01-15

Have you tried more conservative (slower) FMC timing settings with the F427 variant ?

cxiao.6 · ‎2020-02-27

I found the cause of the problem. I used mode 1 before. When the chip selection was switched from norflsah to SRAM, there was an intermediate level in the bus. I don't know why the 407 chip didn't have this problem, but 427 did. Now I change to avoid reading data during this intermediate level

waclawek.jan · ‎2020-02-28

I don't quite understand the cause of your problem (appears to be both devices fighting for the bus, but why, once chipselects don't overlap?), but there are definitively differences in timing of FSMC in 'F40x and FMC in 'F42x, in what appears to be an identical setup https://community.st.com/s/question/0D50X0000C23GN6SQM/f427-fmc-vs-f407-fsmc-different-behaviour-for-backtoback-writes-to-the-same-sram-bank .

JW