Hi Everyone, How to average ADC values in STM32F103VBTx using DMA method?

[sne_123]

I am using STM32F103VBTx. I have configured ADC using DMA method. We are getting some noise on PCB due to which ADC values are not captured properly. We see a lot of variations even after Calibrating ADC values through software. We are trying to eliminate the noise in hardware but what is the best way to calculate average of ADC values captured in DMA method??

[Ozone]

> ... but what is the best way to calculate average of ADC values captured in DMA method??

There is none. DMA is "dumb" hardware that moves memory content from A to B.

You need code for the averaging, preferably attached to the DMA TC interrupt.

> We are getting some noise on PCB due to which ADC values are not captured properly. We see a lot of variations even after Calibrating ADC values through software.

Are you sure the sampling time is sufficient ?

A too short sampling time - or inappropriately high input impedance - would cause similar issues.

[sne_123]

@Ozone​ 

I have tried setting all the possible configurations like :-

ADC_SAMPLETIME_1CYCLE_5         

ADC_SAMPLETIME_7CYCLES_5   

ADC_SAMPLETIME_13CYCLES_5  

ADC_SAMPLETIME_28CYCLES_5   

ADC_SAMPLETIME_41CYCLES_5  

ADC_SAMPLETIME_55CYCLES_5  

ADC_SAMPLETIME_71CYCLES_5   

ADC_SAMPLETIME_239CYCLES_5

But the results are same.

The firmware was working perfectly on STM32F103RB eval nucleo board without any issue. But in our designed PCB we are getting fluctuations.

[oeliks]

Walking avarage is best for dynami​c changing signal. While arithmetic avarage is ok for slof fluctuating signals.

[sne_123]

@oeliks​  What is walking average??

[oeliks]

​In english its called different apparently

https://en.m.wikipedia.org/wiki/Moving_average

Speed of avarage response depends on buffer size.

1)Get 5 samples, add them->sum, divide to avarage 2) add + another sample to​ sum, and " - " first sample, divide sum - to get avarage ... 3)and so on

​But best way is to fight with noise in hardware.

[sne_123]

The ADC clock is set to 12MHz. So for ADC_SAMPLETIME_239CYCLES_5 the sampling time will be (239.5+12)/12 = 20.95us. Am I correct?? or it will be 239.5/12 = 19.95us

Sorry but I am a naive in ADC.

[sne_123]

Ya we are trying to eliminate it through hardware also.

[Ozone]

Sampling time, in STM32 context, is the number of ADC clock cycles the Sample&Hold capacitor is connected to the specific input channel.

I suggest to validate your ADC hardware and routines by checking individual channels first.

Or, apply a known voltage to one channel, and 0V to the others.

For averaging, you will find plenty of examples on the net, just drop the "STM32" or "Cortex M" from the search context.

This algorithms are not platform-specific.