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STM32L4+ OCTOSPI Memory-Mapped mode Read-Write

STrop
Associate II

Hello,

I'm am using the STM32L4R9I-DISCOVERY board with external FLASH memory using OCTOSPI.

I wan't to use it if possible in memory-mapped mode to read and write as a persistent storage

According to the STM32L4+ documentation RM0432 (1) it is possible to use the external Macronix flash memory has memory mapped using OCTOSPI for Read-Write en Execution

According another STMicro slide for STM32L4+ Octospi (2) (slide 6), the memory mapped mode only support Read instruction

The BSP Example for STM32L4R9I-DISCOVERY make use of HAL Function for write operation, switch the OCTOSPI configuration to Memory Mapped in one read operation but never perform write in Memory Mapped mode

Is it possible to perform both read and write with OCTOSPI in Memory Mapped mode ?

(1) https://www.st.com/content/ccc/resource/technical/document/reference_manual/group0/81/c8/d7/84/ba/20/48/5f/DM00310109/files/DM00310109.pdf/jcr:content/translations/en.DM00310109.pdf

(2) https://www.st.com/content/ccc/resource/training/technical/product_training/group0/fd/49/71/1b/2c/22/46/ba/STM32L4Plus_Peripheral_OctoSPI/files/STM32L4Plus_Peripheral_OctoSPI.pdf/jcr:content/translations/en.STM32L4Plus_Peripheral_OctoSPI.pdf

2 REPLIES 2
Andreas Bolsch
Lead II

A write to NOR flash doesn't work in the same way as a read: First, WE bit must be set by a separate command (and it is cleared automatically after completion of programming of a page). Second, writes are page based, i.e. the uppermost address bits must not change during a page programming operation. Third, loading the page's data is completed and programming started by releasing NCS, so this must happen at a well-defined point. Forth, after starting a page write, the flash's busy bit must be polled by read status register operations to find out when the programming has actually finished.

So theoretically, it might be possible to use memory mapped write for NOR flash, however, it would be quite complicated, the OCTOSPI would have to be reconfigured several times from memory-mapped to indirect read/write and vice versa for each page. Not really feasible ...

For SPI-RAM or FRAM it's different, though.

Agreed, for OCTO RAMs sure, the read/write doesn't have much latency. When it's a slow memory (write), HW assist doesn't pay off vs SW implementation.

No need to accelerate the wait...