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STM32F334 Tim3 Prescaler

TA1
Associate III

Dear all,

I am in difficulty to adjust Timer 3. Let me explain with examples:

Internal Clock is 72 MHz and it is used for also Timer 3 as an input clock.

1- When PSC: 36 and ARR: 124 it should generate an interrupt every 62,5 us (we can assume it generates exactly every 62,5us because there is tolerance due to crystal oscillator and interrupt latency. One of GPIO toggles when interrupt services and the duration is measured by a scope. Duration is measured about 64 us. We can assume it is acceptable. (72MHz/36 = 2 MHz CLK --> 125/2MHz = 62,5 us, if I do correct calculation)

2- When PSC: 72 and ARR: 77 it should generate an interrupt every 78 us (it is measured 79us with the scope)

3- When PSC: 36 and ARR: 155 it should generate an interrupt every 78 us (it is measured 80us with the scope)

4- When PSC: 18 and ARR: 311 it should generate an interrupt every 78 us (it is measured 82.3 us with the scope)

5- When PSC: 9 and ARR: 623 it should generate an interrupt every 78 us (it is measured 86.5 us with the scope)

Is there any input clock limitation for Timer 3, because if the input clock frequency is more than 2 MHz, I cannot achieve the desired time.

I don't know what it is the problem. It might be a very simple reason but I didn't realize. If someone explains or share a file to let me read and understand, it would be great.

Thank you very much in advance

Regards

1 ACCEPTED SOLUTION

Accepted Solutions
turboscrew
Senior III

Check the reference manual. For F4 series device it says:

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to f CK_PSC / (PSC[15:0] + 1).

View solution in original post

3 REPLIES 3
turboscrew
Senior III

Check the reference manual. For F4 series device it says:

Bits 15:0 PSC[15:0]: Prescaler value

The counter clock frequency CK_CNT is equal to f CK_PSC / (PSC[15:0] + 1).

berendi
Principal

Both PSC and ARR should be one less than the required divisor value, as both counters are counting from 0 to the value in the register. This becomes more apparent when the PSC value is low, because the relative error is higher.

Thank you very much. When I looked at page 484 in the User manual of F334, I assume PSC is 2 or 4 to achive divison ratio. After your explanation PSC should be 1 and 3 accordingly.

Thank you very much..