STM32G071CBT6 LQFP48 package. Internal voltage buffer available? Seems not!

[waclawek.jan]

Why? DS says, VREF+ is on pin 5 in the 48-pin packages, so it's not bonded to VDDA, so the internal voltage buffer should be available.

JW

[KBaer]

Hi Jan,

in this case VRR should go high after settling, but it stays low for ever? Here is the code:

VREFBUF->CSR = 0x000000003;   // ...00000011 VRS=0, HIZ=1, ENVR=1 => VREF = 2.048V

while ((VREFBUF->CSR & 0x00000008) == 0);      // Wait until VRR = 1 => VREF Buffer ready

If I use the default setting and VREF+ pin (5) = VDDA = 3.3V all works correctly if I do not wait for VRR.

VREFBUF->CSR = 0x000000006;   // ...00000110 VRS=1, HIZ=1, ENVR=0 => VREF = VREF+PIN

But the internal 2.048V or 2.500V VREF Buffer does not work at all?

[waclawek.jan]

JW

[KBaer]

Hi Jan,

yes I tried this too. Here is the code:

   VREFBUF->CSR = 0x000000001;   // ...00000001 VRS=0, HIZ=0, ENVR=1 => VREF, VREF+Pin = 2.048V

   //VREFBUF->CSR = 0x000000005;   // ...00000101 VRS=1, HIZ=0, ENVR=1 => VREF, VREF+Pin = 2.500V

But in this case VREF+ Pin is connected to the internal VREF Buffer. So I diconnected the external voltage at pin VREF+(5) =3.3V.

Again VRR stays low for ever and neither 2.048V nor 2.500V appear on the VREF+(5) pin to be available for ratiometric measurements?

[Tesla DeLorean]

Is it necessary to debug this through a key-hole ?

Perhaps it is other code upstream that's failing? Post enough code so a stand-alone independent test can be done by ST, or whomever.

Try checking clocks and other dependencies, units enabled, PLLs, etc.

Inspect HAL sources to see if any expectations or sequences, in/across multiple registers. Even if you don't care to use that code yourself.

[waclawek.jan]

Did you read back the value from VREFBUF->CSR in debugger or otherwise, and check the bits you've set/cleared?

Do you have clock enabled in RCC_APBENR2.SYSCFGEN?

JW

[KBaer]

Hi Jan,

first of all thank you for your support. I actually forgot to set RCC_APBENR2.SYSCFGEN = 1.

If I now read VREFBUF.CSR there are the correct values for VRS, HIW and ENVR.

I thought it would work now but unfortunately not. VRR still remains at 0 and the code stops here.

If I comment the while loop the ADC works fine but its values refers to the 3.3V voltage applied to VREF+Pin and not to the internal 2.048V or 2.500V.

Also a reset at the beginning or some software wait loops for settling does not change anything.

void init_vref(void)

{

   // Enable the peripheral clock, otherwise we cannot access the registers!

   RCC->APBRSTR2 |= 0x00000001;   // SYSCFGRST = 1 => SYSCFG, COMP and VREFBUF reset

   RCC->APBENR2 |= 0x00000001;    // SYSCFGEN = 1 => SYSCFG, COMP and VREFBUF clock enable

   //VREFBUF->CSR = 0x000000002; // ...00000010 VRS=0, HIZ=1, ENVR=0 => VREF = VREF+PIN

   //VREFBUF->CSR = 0x000000006; // ...00000110 VRS=1, HIZ=1, ENVR=0 => VREF = VREF+PIN

   VREFBUF->CSR = 0x000000003; // ...00000011 VRS=0, HIZ=1, ENVR=1 => VREF = 2.048V

   //VREFBUF->CSR = 0x000000007; // ...00000111 VRS=1, HIZ=1, ENVR=1 => VREF = 2.500V

   //VREFBUF->CSR = 0x000000001; // ...00000001 VRS=0, HIZ=0, ENVR=1 => VREF, VREF+Pin = 2.048V

   //VREFBUF->CSR = 0x000000005; // ...00000101 VRS=1, HIZ=0, ENVR=1 => VREF, VREF+Pin = 2.500V

   xxTest = VREFBUF->CSR; // xxTest = universal test variable displayed on the LCD, here = 3 (2.048V)

   //while ((VREFBUF->CSR & 0x00000008) == 0);   // Wait until VRR = 1 => VREF Buffer ready

}

[Antoine Odonne]

Hello,

The SYSCFG reset bit must be cleared in RCC APBRSTR2, it is active as long as set.

"If I comment the while loop the ADC works fine but its values refers to the 3.3V voltage applied to VREF+Pin and not to the internal 2.048V or 2.500V."

You confirm that no supply is connected on VREF+ when trying to switch ON the buffer? Just the capacitance?

Regards,

Antoine

[KBaer]

Bonjour Antoine,

normally my code starts with RCC->APBENR2 |=... => the SYSSCFG reset bit = 0

Now I can write to CSR and when I read it back its OK.

VREF+Pin is connected via a ferrit with VDD/VDDA (3.3V) as long as HIZ = 1 (Default).

Only if I set HIZ = 0 I disconnect VREF+ from VDD/VDDA because I believe that should result in a short circuit

with the internal VREF buffer?

But in all cases VRR remains low and the ADC results always refers to 3.3V if VREF+Pin is connected with VDD/VDDA.

If I disconnect the VREF+Pin (Floating) the ADC results are random in all cases. The internal buffer is never the reference.