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BLE_HeartRateFreeRTOS example located in STM32Cube_FW_WB_V1.3.0 (CubeMX 5.4) doesn't work

Micha Valach
Associate III

I reopen this issue under the correct place with correct Topic as STM32WB !

I comiled the BLE_HeartRateFreeRTOS project example located at STM32Cube_FW_WB_V1.3.0 (CubeMX 5.4) as CubeIDE (1.1.0) project,

However the project start running then stucked inside the procedure osKernelStart();

seems, received an WWDG interrupt (see attached snapshot)0690X00000ArnJrQAJ.jpg

although the WWDG compile flag is remarked /*#define HAL_WWDG_MODULE_ENABLED  */

Any Idea?

Thanks In Advance,

Micha

3 REPLIES 3
~Amit~
Associate III

any solution for this?

I am having the same issue when initiating a cube project.

using:

  1. cube version 5.6.0
  2. STM32Cube_FW_WB_V1.5.0
  3. Atollic true studio version 9.3.0

Micha Valach
Associate III

Hi Amit,

Seems the existing code, for this project is working fine!

You can generate code from the BLE_HeartRateFreeRTOS.ioc in a separate director (this is the where the original code was taken - this code has some errors) and compare it to existing working code.

Thanks,

Micha

Micha Valach
Associate III

Hi Amit,

The above problem occur due to a missing handler in the stm32wbxx_it.c file

In order to resolve it, please see an article in freeRTOS website, located at: https://www.freertos.org/Debugging-Hard-Faults-On-Cortex-M-Microcontrollers.html

You need to add some ASM lines (see below)

Default_Handler:

 /* Load the address of the interrupt control register into r3. */

 ldr r3, NVIC_INT_CTRL_CONST

 /* Load the value of the interrupt control register into r2 from the address held in r3. */

 ldr r2, [r3, #0]

 /* The interrupt number is in the least significant byte - clear all other bits. */

 uxtb r2, r2 /* put Break Point (PKBT) here and watch the value in register R2 , this will be the offset in the g_pfnVectors table (see below)

Infinite_Loop:

 /* Now sit in an infinite loop - the number of the executing interrupt  is held in r2. */

 b Infinite_Loop

 .size Default_Handler, .-Default_Handler

.align 4

/* The address of the NVIC interrupt control register. */

NVIC_INT_CTRL_CONST: .word 0xe000ed04

g_pfnVectors:

 .word _estack /* 0 */

 .word Reset_Handler /* 1 */

.word NMI_Handler /* 2 */

 .word HardFault_Handler /* 3 */

 .word MemManage_Handler /* 4 */

 .word BusFault_Handler /* 5 */

 .word UsageFault_Handler /* 6 */

 .word 0

 .word 0

 .word 0

 .word 0

 .word SVC_Handler

 .word DebugMon_Handler

 .word 0

 .word PendSV_Handler

 .word SysTick_Handler

 .word WWDG_IRQHandler

 .word PVD_PVM_IRQHandler

 .word TAMP_STAMP_LSECSS_IRQHandler

 .word RTC_WKUP_IRQHandler

....