2019-11-04 03:49 PM
We use STM32F767NIH and see random QSPI interface failure accessing a micron flash. The failure happens when we run diagnostic sw in a loop that does a write, read back and verify function. Using a protocol analyzer, we notice that when the QSPI fails (during read), CS pin going high a few times. Is this normal?
2019-11-04 05:00 PM
2019-11-04 05:34 PM
2019-11-04 05:57 PM
It appears that the memory does not "see" those pulses on CS, as it keeps outputting what appears to be reasonable data on all four data pins.
This, together with similar suspiciously short pulses on data, might indicate problematic LA attachment.
JW
PS. Please change your username to a normal nick.
2019-11-04 06:06 PM
Definitely some weirdness, D3 being LOW is odd. Would check that the memory/CPU have a common understanding about being in QPI mode.
I tend to check in 1-bit, 2-bit and then 4-bit mode. Write patterns that will exercise all 4-bits. Perhaps pick some where the high/low nibble have different states.
If it is doing a long burst 0x6B read, I wouldn't expect the CS to glitch unless there was some cross-talk, or cross-wiring.
You see this on ST boards, or just the custom board?
2019-11-04 06:25 PM
It's custom board.
2019-11-04 06:39 PM
2019-11-04 07:12 PM
> D3 being LOW is odd.
Indeed, and I did not notice that. Also, on the second screenshot, the pulses on CS appear roughly where D3 ought to pulse, if the data pattern is simply a sequence of 0-1-2-....
D3 shorted to a neighbouring pin/track?
JW
2019-11-08 04:38 PM
2019-11-08 05:00 PM