cancel
Showing results for 
Search instead for 
Did you mean: 

DDR3L, bit swap inside bytes. How to configure it ?

Jboui.450
Associate

i read the following information in the doc AN5122 :

Standard fly-by topology

A standard fly-by topology is comprised of:

• A distributed A/C bus with 56 Ω on-board termination at VTT (VDD_DDR/2)

• A differential clock, distributed to all of the DDR devices

– Implement a differential termination of the CLK_N/CLK_P signals using one 100 Ω

resistor.

• There must be a point-to-point connection of the data bus (4 swappable bytes, and

swappable bits in the same byte), including:

– 32 data signal bits (DQ)

– 4 data mask signals (DQMx)

– 4 differential clocks (DQSx_N/DQSx_P)

i would like for the ease of layout swap bit inside byte0 and byte1 of control signals but i dont see any where how to inform the system and set configuration for the bit swap.

Can you point me to a document where it is explain how to setup bit swap configuration ?

Tanks for support

Julien.

1 REPLY 1
PatrickF
ST Employee

Hello,

you don't need any system configuration when you swap bits inside same byte or even byte Vs byte.

For data, bit and byte numbering on a memory is only a matter of give them unique name, in all cases, you read the bit data on same wire you write it.

This swaps are possible on DDR3/DDR3L as there is no memory register configuration using data lines (configuration uses address/command lanes).

On LPDDR2/LPDDR3, there is some constrains for Byte0 (no bit swap, no byte swap) as it is used to access internal registers.

In order to give better visibility on the answered topics, please click on 'Accept as Solution' on the reply which solved your issue or answered your question.