Output Compare Mode for STM32F407 Discovery board

[Kumar B]

Hi,

I am working on STM32F4 discovery board and I am trying to use output compare mode.

and I have written the following code using peripheral registers.

The application is Toggle the LED for every 1sec when output compare is matched.

Here is the code. But it is not working. Can any one help me what might be the problem

/*This Program demonstrate the working of General Purpose Timer using Output Compare @1Hz Delay*/
 
#include "stm32f4xx.h" //Header File for STM32F4 device
 
int main(void)
{
	//
	RCC->AHB1ENR |=1;          //Enable GPIOA Port Clock	
	GPIOA->MODER|= 0X800 ;      //Configure I/O direction for PA5 as Alternatefunction   0100 0000 0000 
	GPIOA->AFR[0]|=0X00100000;
	RCC->APB1ENR|=1;
	TIM2->PSC=1600-1;
	TIM2->ARR=10000-1;
	TIM2->CCMR1=0X30;
	TIM2->CCR1=0;
	TIM2->CCER|=1;
	TIM2->CNT=0;
	TIM2->CR1=1;
	
	while(1)
	{
		
		
	}
		
	return 0;	
}

[waclawek.jan]

> TIM2->CCR1=0;

This results in a zero-length pulse (i.e. no pulse).

[EDIT] Spoke too soon. Now I see you use Toggle. Then I don't know...

[EDIT2] It works for me, exactly as written, on a DISCO429. Read out and check the relevant registers content in a debugger.

JW

[berendi]

Check the errata document.

2.1.13 Delay after an RCC peripheral clock enabling

Description

A delay between an RCC peripheral clock enable and the effective peripheral enabling

should be taken into account in order to manage the peripheral read/write to registers.

This delay depends on the peripheral mapping:

• If the peripheral is mapped on AHB: the delay should be equal to 2 AHB cycles.

• If the peripheral is mapped on APB: the delay should be equal to 1 + (AHB/APB

prescaler) cycles.

Workarounds

1. Use the DSB instruction to stall the Cortex®-M4 CPU pipeline until the instruction is

completed.

2. Insert “n�? NOPs between the RCC enable bit write and the peripheral register writes (n = 2 for AHB peripherals, n = 1 + AHB/APB prescaler in case of APB peripherals).

3. Or simply insert a dummy read operation from the corresponding register just after

enabling the peripheral clock.

I'd simply rearrange RCC accesses in a way that there'd be something else between enabling a peripheral and using it

RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;          //Enable GPIOA Port Clock	
RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
GPIOA->MODER |= 0X800 ;      //Configure I/O direction for PA5 as Alternatefunction   0100 0000 0000 
GPIOA->AFR[0] |= 0X00100000;
TIM2->PSC=1600-1;

[Kumar B]

Thanks for the reply. I have tried the above snippet and it's not working. Let me know if any thing is required.

[waclawek.jan]

Read out and check the relevant registers content in a debugger.

You can also try to set the pin as GPIO and toggle the pin "manually", to exclude hardware problem.

JW